Branislav Mados

Intrusion detection system based on system behavior

This work aims to designing and implementing own intrusion detection system based on system behavior. The main component of this system used in analysis and later in implementation is widely used against defending to another type of crime. Presumption that some techniques are well working against particular type of computer criminality leads to using those techniques against another type of computer criminality. An intrusion detection systems based on system behavior in general evaluates the behavior of observed system. Therefore the level of system observation is very important. We propose intrusion detection system that works at low level system observation. This is important because of many malicious codes nowadays mask their behavior and therefore is difficult to expose those malicious codes from user perspective. Proposed intrusion detection system aims to be modular because of achieving further development and also as simple as possible because of better user understanding. The interconnection of existing technologies and solutions and developing new one result to complex intrusion detection system.

Data flow graph mapping techniques of computer architecture with data driven computation model

Article introduces architecture of computer with data driven computation model based on principles of tile computing which is modern approach to multi-core design of microprocessors, with basic principle of cores layout in bi-directional mesh of cores with interconnecting communication network. Special attention is paid to description of data flow graph mapping technique and multi-mapping techniques proposed within this architecture. Hardware implementation of computers prototype with use of Xilinx Spartan 3 PCIe Starter board with Spartan 3 AN FPGA chip is also described. Architecture is developed at the Department of Computers and Informatics, Faculty of Electrical Engineering and Informatics, Technical University of Kosice. The work is one of reached results within projects VEGA 1/4071/07 and APVV 0073–07, being solved at the Department of Computers and Informatics, Faculty of Electrical Engineering and Informatics, Technical University of Košice.

The process control for P-single operators

The architecture described in this article belongs to a class of dynamic data flow architectures, in which the operand process control significantly affects the performance parameters as well as the system characteristics of the given architecture. The main component of the presented architecture is the multifunctional pipeline unit, which handles processing of data tokens representing the instructions of the program. This article describes the pipelined single operand data flow operators process control.

Priority of instructions execution and DFG mapping techniques of computer architecture with data driven computation model

The article introduces proposed computer architecture with data driven computation model based on principles of tile computing as the modern approach to multi-core design of microprocessors. Special attention is paid to the description of characteristics of architecture, which are priority of instructions execution with coloring of instruction priorities, data flow graph mapping technique and multi-mapping technique, which are proposed within this architecture. Architecture is developed at the Department of Computers and Informatics, Faculty of Electrical Engineering and Informatics, Technical University of Košice. The work is one of reached results within projects APVV-0008-10 and KEGA project No. 3/7110/09, being solved at the Department of Computers and Informatics, Faculty of Electrical Engineering and Informatics, Technical University of Košice.

Operand processing and P-single operators

The data flow model of execution offers attractive properties for parallel processing. First, it is asynchronous: Because the readiness of data dictates the instruction execution. Second, it is self-scheduling: The data flow graph representation of a program eliminates the need to explicitly manage parallel execution. The architecture described in this article belongs to a class of dynamic dataflow architectures, in which the operand process control significantly affects the performance parameters as well as the system characteristics of the given architecture.

Artificial neural network based IDS

The Network Intrusion Detection Systems (NIDS) are either signature based or anomaly based. In this paper presented NIDS system belongs to anomaly based Neural Network Intrusion Detection System (NNIDS). The proposed NNIDS is able to successfully recognize learned malicious activities in a network environment. It was tested for the SYN flood attack, UDP flood attack, nMap scanning attack, and also for non-malicious communication.

Brain-computer interface and Arduino microcontroller family software interconnection solution

Brain-Computer Interface (BCI) is the modern approach to the construction of the Human-Machine Interface (HMI) that interconnects human brain and the machine and allows to send commands to the machine directly from the central nervous system (CNS) and especially the brain. Great popularity of the Arduino microcontroller board family and integration of its members into many projects including amateur, professional, industrial and scientific solutions impelled us to design software solution, that helps integrate Brain Computer Interface comprising Emotiv EPOC Neuroheadset with Arduino microcontroller boards. The paper introduces concept of the Brain-Computer Interface in its first section and possibilities of its use. Next section of the paper describes Emotiv EPOC Neuroheadset, which is the part of the BCI, with function of the electroencephalograph (EEG) that non-invasively monitors the electromagnetic manifestations of neural activity of the human central nervous system (CNS), mainly the brain. Using the proprietary software installed on the host computer software transforms acquired signals into the commands that are then executed via third party software. Another part of the paper introduces Arduino microcontroller board family and the last part describes proposed software solution that provides software interface between Emotiv EPOC Neuroheadset software and Arduino microcontroller boards.

The CASE tool for programming of the multi-core System-on-a-Chip with the data flow computation control

The paper describes Computer Aided Software Engineering (CASE) tool, that supports programming of the experimental multi-core tile based System-on-a-Chip (SoC). SoC comprises cores, which are based on the data flow computation control principle. Proposed CASE tool allows creation of the program code in graphical form using Data Flow Graph (DFG) or in text representation using assembly language or machine code. Automatic transformations between those representations are supported. CASE tool brings sequential, mask based and global multi-mapping of the program code, which was introduced in our previous research. Another output lies in introduction of altered assembly language and machine code that allow multi-mapping of the program code on the instructions level. The aim of the solution lies in optimization of the program load phase in multi-core microprocessors that comprise tens or potentially hundreds of cores.

P-Single Operators in Pipeline System of DF-KPI Architecture

There has been a resurgence of interest in data flow architectures, because the dataflow model of execution offers attractive properties for parallel processing. In data flow architectures the computing process is managed by the operands flow accessed on different levels for executing instructions of dataflow program. Data flow architectures have been traditionally classified as either static or dynamic. The architecture described in this article belongs to a class of dynamic data flow architectures, in which the operand process control significantly affects the performance parameters as well as the system characteristics of the given architecture. From the many types of operators, this article provides microprogram managing for P-single operators in pipeline system of DF-KPI architecture.

Modeling of intelligent calculations in cubic network of workstations

Article describes model of computation with feedforward multilayer neural network implemented in the network of workstations with cubic topology. Presented computation model is based on parallel error backpropagation algorithm with regard to characteristics of simulations implementation architecture. Effectivity of parallel implementation of feedforward multilayer neural network is represented trough the cost of computation in parallel environment of workstations. Designed computation model allows formally describe components of parallel implementation of neural network. Model provides mathematical instrument for verification of performance, used in simulation of feedforward multilayer neural network on specified hardware platform.