Anton Blad

Architectures for cognitive radio testbeds and demonstrators — An overview

Wireless communication standards are developed at an ever-increasing rate of pace, and significant amounts of effort is put into research for new communication methods and concepts. On the physical layer, such topics include MIMO, cooperative communication, and error control coding, whereas research on the medium access layer includes link control, network topology, and cognitive radio. At the same time, implementations are moving from traditional fixed hardware architectures towards software, allowing more efficient development. Today, field-programmable gate arrays (FPGAs) and regular desktop computers are fast enough to handle complete baseband processing chains, and there are several platforms, both open-source and commercial, providing such solutions. The aims of this paper is to give an overview of five of the available platforms and their characteristics, and compare the features and performance measures of the different systems.

An early decision decoding algorithm for LDPC codes using dynamic thresholds

Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate a modification to the decoding algorithm, using early decisions for bits with high reliabilities. This reduces the amount of messages passed by the algorithm, which can be expected to reduce the switching activity of a hardware implementation. While direct application of the modification results in severe performance penalties, we show how to adapt the algorithm to reduce the impact, resulting in a negligible decrease in error correction performance.

Spectrum sensing of OFDM signals in the presence of CFO: New algorithms and empirical evaluation using USRP

In this work, we consider spectrum sensing of OFDM signals. We deal with the inevitable problem of a carrier frequency offset, and propose modifications to some state-of-the-art detectors to cope with that. Moreover, the (modified) detectors are implemented using GNU radio and USRP, and evaluated over a physical radio channel. Measurements show that all of the evaluated detectors perform quite well, and the preferred choice of detector depends on the detection requirements and the radio environment.

Bit-level optimized FIR filter architectures for high-speed decimation applications

Analog-to-digital converters based on sigma-delta modulation have shown promising performance, with steadily increasing bandwidth. However, associated with the increasing bandwidth is an increasing output sample rate, which becomes costly to decimate in the digital domain. Commonly, cascaded integrator comb structures have been used for the first decimation stage, but polyphase decomposed FIR filter architectures have been shown to be more power efficient. In this paper, a bit-level optimization algorithm is introduced, and applied to the direct form and transposed form FIR filter architectures. Mainly, two conclusions can be drawn. The transposed architecture has significantly lower complexity in most circumstances, and the inability to implement an efficient adder prohibits the symmetry of the filter coefficients to be used efficiently for the direct form architecture.

A General Formulation of Analog-to-Digital Converters Using Parallel Sigma-Delta Modulators and Modulation Sequences

A formulation based on multirate theory is introduced for analog-to-digital converters using parallel sigma-delta modulators in conjunction with modulation sequences. It is shown how the formulation can be used to analyze a systems sensitivity to channel mismatch errors by means of circulant and pseudo-circulant matrices. It is demonstrated how the time-interleaved-modulated (TIM), Hadamard-modulated (HM) and frequency-band decomposition (FBD) converters can be viewed as special cases of this more general description, and it is shown why the TIM and HM ADCs are sensitive to channel mismatch errors, whereas the FBD ADCs are not

FPGA implementation of rate-compatible QC-LDPC code decoder

The use of rate-compatible error correcting codes offers several advantages as compared to the use of fixed-rate codes: a smooth adaptation to the channel conditions, the possibility of incremental Hybrid ARQ schemes, as well as simplified code representations in the encoder and decoder. In this paper, the implementation of a decoder for rate-compatible quasi-cyclic LDPC codes is considered. The decoder uses check node merging to increase the convergence speed of the algorithm. Check node merging allows the decoder to achieve the same performance with a significantly lower number of iterations, thereby increasing the throughput. The feasibility of a check node merging decoder is investigated for codes from IEEE 802.16e and IEEE 802.11n. The faster convergence rate of the check node merging algorithm allows the decoder to be implemented using lower parallelization factors, thereby reducing the logic complexity. The designs have been synthesized to an Altera Cyclone II FPGA, and results show significant increases in throughput at high SNR.

Redundancy reduction for high-speed fir filter architectures based on carry-save adder trees

In this work we consider high-speed FIR filter architectures implemented using, possibly pipelined, carry-save adder trees for accumulating the partial products. In particular we focus on the mapping between partial products and full adders and propose a technique to reduce the number of carry-save adders based on the inherent redundancy of the partial products. The redundancy reduction is performed on the bit-level to also work for short wordlength data such as those obtained from sigma-delta modulators.

An RF Sampling Radio Frontend Based on ΣΔ-Conversion

An RF frontend based on /slp Sigma/Δ-conversion at RF sampling frequency is explored. We discuss the requirements and propose and evaluate possible architectures through simulations. The feasibilities of the practical implementations of the proposed solutions are discussed

Multirate formulation for mismatch sensitivity analysis of analog-to-digital converters that utilize parallel ΣΔ-modulators

A general formulation based on multirate filterbank theory for analog-to-digital converters using parallel sigmadelta modulators in conjunction with modulation sequences is presented. The time-interleaved modulators (TIMs), Hadamard modulators (HMs), and frequency-band decomposition modulators (FBDMs) can be viewed as special cases of the proposed description. The usefulness of the formulation stems from its ability to analyze a systems sensitivity to aliasing due to channel mismatch and modulation sequence level errors. Both Nyquist-rate and oversampled systems are considered, and it is shown how the matching requirements between channels can be reduced for oversampled systems. The new formulation is useful also for the derivation of new modulation schemes, and an example is given of how it can be used in this context.

Rate-compatible LDPC code decoder using check-node merging

The use of rate-compatible error correcting codes offers several advantages as compared to the use of fixed-rate codes: a smooth adaptation to the channel conditions, the possibility of incremental Hybrid ARQ schemes, as well as sharing of the encoder and decoder implementations between the codes of different rates. In this paper, the implementation of a decoder for rate-compatible quasi-cyclic LDPC codes is considered. Assuming the use of a code ensemble obtained through puncturing of a low-rate mother code, the decoder achieves significantly reduced convergence rates by merging the check node neighbours of the punctured variable nodes. The architecture uses the minsum algorithm with serial node processing elements to efficiently handle the wide spread of node degrees that results from the merging of the check nodes.