Anton J. Bauer

Tunneling atomic-force microscopy as a highly sensitive mapping tool for the characterization of film morphology in thin high-k dielectrics

High-k dielectric layers (HfSixOy and ZrO2) with different film morphologies were investigated by tunneling atomic-force microscopy (TUNA). Different current distributions were observed for amorphous and nanocrystalline films by analyzing TUNA current maps. This even holds for crystalline layers where highly resolved atomic-force microscopy cannot detect any crystalline structures. However, TUNA enables the determination of morphology in terms of differences in current densities between nanocrystalline grains and their boundaries. The film morphologies were proven by high-resolution transmission electron microscopy. The investigations show TUNA as powerful current mapping tool for the characterization of morphology in thin high-k films on a nanoscale.

Different current conduction mechanisms through thin high-kHfxTiySizO films due to the varying Hf to Ti ratio

We have investigated the electrical behavior of high permittivity (high-k) hafnium–titanium–silicate (HfxTiySizO) layers with different Hf:Ti ratios in the films. The films are prepared by metalorganic chemical vapor deposition using a mixture of two single source precursors. Oxide and interface charges, leakage currents and conduction mechanisms are found to be a strong function of the film composition. The films with Hf content less than 10 at. % show lower levels of oxide and interface charges and higher dielectric constant whereas those with Hf content higher than 15 at. % have better leakage current properties. A strong evidence is presented that in films with Hf content lower than 10 at. % the conduction process is governed by a phonon-assisted tunneling, i.e., it is defined rather by the intrinsic properties of the material than by its defect structure.

Improved insight in charge trapping of high-k ZrO2/SiO2 stacks by use of tunneling atomic force microscopy

In this work, tunneling atomic force microscopy (TUNA) is used to describe the charge trapping in high-k ZrO2 dielectric stacks at nanoscale dimensions by analyzing the alteration of the I-V curves and the I-V hysteresis phenomena with repeated measurements (up to 100 curves) at a single spot of only several nm2 in area. TUNA is also suggested as a powerful technique to correlate the electrical characteristics to the physical properties of the stacks. In particular, the influence of the thin SiO2 interfacial layer thickness and its modification with annealing conditions on the electrical properties is demonstrated. Furthermore, the appearance of an I-V hysteresis and its relation to degradation mechanisms in high-k dielectric stacks are explained. Trapping at pre-existing traps is evidenced.

Investigation of the reliability of 4H–SiC MOS devices for high temperature applications

Abstract In this paper, the excellent reliability of 4H–SiC MOS devices during high temperature operation is demonstrated for a gate oxide processed in N 2 O. A temperature dependent Fowler–Nordheim analysis is used to show that statistical energy spreading accounts for only part of the reported temperature induced barrier height degradation. Poole–Frenkel current caused by acceptor like traps in the oxide due to carbon interstitials is proposed to be responsible for the additional current observed. Temperature and electric field acceleration of the time to dielectric breakdown is investigated at elevated temperatures in order to predict the expected MOS lifetime during high temperature operation.

Comprehensive study of focused ion beam induced lateral damage in silicon by scanning probe microscopy techniques

Scanning probe microscopy techniques and, in particular, scanning spreading resistance microscopy (SSRM) were used for a detailed characterization of focused ion beam (FIB) induced damage in the surrounding of purposely irradiated areas on silicon. It is shown that the damaged area detected using these techniques extends up to several micrometers around the irradiated structures. The influence of the key FIB processing parameters on the FIB induced damage was examined. Parameters which were taken into account are the ion dose (from 1012 to 1018 cm−2), the milled structure size (circle diameters from 0.25 to 10 μm), the beam energy (from 10 to 30 keV), and the beam current (from 1.5 to 280 pA). Moreover, the influence of the SSRM settings on the measurement results was investigated. Settings which were considered are the bias voltage and the force applied to the tip during the SSRM analysis. High resolution transmission electron microscopy and secondary ion mass spectroscopy analyses were performed to vali...

Structural properties of as deposited and annealed ZrO2 influenced by atomic layer deposition, substrate, and doping

Thin ZrO2 films are of high interest as high-k material in dynamic random access memory (DRAM), embedded dynamic random access memory, and resistive random access memory as well as for gate oxides. Actually, ZrO2 is predicted to be the key material in future DRAM generations below 20 nm. Profound knowledge of pure and doped ZrO2 thin films, especially of the structural properties, is essential in order to meet the requirements of future devices. This paper gives a detailed overview about the structural properties of ZrO2 films in dependence of various process parameters. The study of atomic layer deposition (ALD) growth mechanisms of ZrO2 on a TiN-substrate in comparison to a Si-substrate covered with native oxide exhibits significant differences. Furthermore, the structural properties crystallinity, surface roughness, and film stress are studied after the ALD deposition in dependence of the process parameters deposition temperature, layer thickness, and underlying substrate. Remarkable dependencies of the ZrO2 crystallization temperatures on the substrates are figured out. The structural properties after various annealing steps are monitored as well. The influence of doping by SiO2 and Al2O3 is studied, which is primarily used to keep the thin films amorphous during deposition.

Reduced On Resistance in LDMOS Devices by Integrating Trench Gates Into Planar Technology

In this letter, we report on the reduction of device resistance by up to 36% in lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistors by incorporating trench gates into conventional planar technology. The process and device simulations of this novel device topology are based on a state-of-the-art LDMOS field-effect transistor with a reduced-surface-field extension (buried p-well) for high-voltage applications used for standard IC and ASIC manufacturing processes. Because the well implants can remain unchanged, only a few additional process steps are required for manufacturing such a device. By a straightforward combination of trench- with planar-gate topology, the device resistance can be reduced from 145 to 94 m¿·mm2 for the underlying 50-V LDMOS device while fully maintaining its specified blocking properties. The depth of the trench gates just slightly influences the electrical device properties, demonstrating the robustness of trench-gate integration into an existing planar-gate technology.

New Single‐Source Precursors for the MOCVD of High‐κ Dielectric Zirconium Silicates to Replace SiO2 in Semiconducting Devices

Two new single-source zirconium silicate precursors Zr(acac) 2 (OSiMe 3 ) 2 A, and Zr(acac) 2 (OSi t BuMe 2 ) 2 B, have been synthesized. The stability and vapor pressure of the two compounds were investigated. They have been used to deposit films of Zr 1-x Si x O 2 by metal-organic (MO)CVD in the temperature range 400-700 °C. Zirconium silicate films with very low carbon contamination and silicon content, x, in the range 0.05-0.25 have been obtained. The two precursors differ, by a factor of two, in activation energy for the MOCVD of films (63 kJ mol -1 for A, and 145 kJ mol -1 for B), and differential scanning calorimetry (DSC) shows they have quite different decomposition temperatures. The film composition was determined by X-ray photoelectron spectroscopy (XPS) and the crystallinity of the layers was studied by X-ray diffraction (XRD). Preliminary electrical characterizations of the zirconium silicate films were conducted on MOS capacitors with Al as gate electrodes. The experiments exhibit the generation of negative charges in the layers during the measurements, shown by a large hysteresis in the CV curves and a shift of the IV curves from the first to the following measurements. Low leakage current densities in the lower voltage regime are observed.

Detailed leakage current analysis of metal–insulator–metal capacitors with ZrO2, ZrO2/SiO2/ZrO2, and ZrO2/Al2O3/ZrO2 as dielectric and TiN electrodes

ZrO2-based metal–insulator–metal capacitors are used in various volatile and nonvolatile memory devices as well as for buffer capacitors or radio frequency applications. Thus, process optimization and material tuning by doping is necessary to selectively optimize the electrical performance. The most common process for dielectric fabrication is atomic layer deposition which guarantees high conformity in three dimensional structures and excellent composition control. In this paper, the C–V and J–V characteristics of ZrO2 metal–insulator–metal capacitors with TiN electrodes are analyzed in dependence on the O3 pulse time revealing the optimum atomic layer deposition process conditions. Moreover, a detailed study of the leakage current mechanisms in undoped ZrO2 compared to SiO2- or Al2O3-doped ZrO2 is enclosed. Thereby, the discovered dependencies on interfaces, doping, layer thickness, and crystalline phases enable the detailed understanding and evaluation of the most suitable material stack for dynamic ra...

Influence of the amorphous/crystalline phase of Zr1−xAlxO2 high-k layers on the capacitance performance of metal insulator metal stacks

The capacitance behavior of metal insulator metal (MIM) structures with Zr1−xAlxO2 dielectrics and TiN metal electrodes is analyzed. The capacitance nonlinearity, the dielectric relaxation, and the loss phenomena are found to depend strongly on the Al content, the dielectric thickness, and the amorphous/crystalline phase of the dielectric layer. Two different kinds of phenomena—crystallization-related and interface-related, are considered to explain the observed results, especially the polarity asymmetry in the dielectric behavior. It is found that crystallization of the films enhances the effects of dielectric relaxation and loss, most likely due to charge trapping at grain boundaries. Further on, reactions between the oxidizing ambient (ozone) and the bottom electrode during high-k deposition result in structural changes (formation of TiOx interfacial layer) and thus in generation of defects which cause a different electrical behavior of the two TiN/Zr1−xAlxO2 interfaces at the top and the bottom electr...