Martin Rambach

Nanoscale structural characterization of epitaxial graphene grown on off-axis 4H-SiC (0001)

In this work, we present a nanometer resolution structural characterization of epitaxial graphene (EG) layers grown on 4H-SiC (0001) 8° off-axis, by annealing in inert gas ambient (Ar) in a wide temperature range (Tgr from 1600 to 2000°C). For all the considered growth temperatures, few layers of graphene (FLG) conformally covering the 100 to 200-nm wide terraces of the SiC surface have been observed by high-resolution cross-sectional transmission electron microscopy (HR-XTEM). Tapping mode atomic force microscopy (t-AFM) showed the formation of wrinkles with approx. 1 to 2 nm height and 10 to 20 nm width in the FLG film, as a result of the release of the compressive strain, which builds up in FLG during the sample cooling due to the thermal expansion coefficients mismatch between graphene and SiC. While for EG grown on on-axis 4H-SiC an isotropic mesh-like network of wrinkles interconnected into nodes is commonly reported, in the present case of a vicinal SiC surface, wrinkles are preferentially oriented in the direction perpendicular to the step edges of the SiC terraces. For each Tgr, the number of graphene layers was determined on very small sample areas by HR-XTEM and, with high statistics and on several sample positions, by measuring the depth of selectively etched trenches in FLG by t-AFM. Both the density of wrinkles and the number of graphene layers are found to increase almost linearly as a function of the growth temperature in the considered temperature range.

Electrical Characterization of Al Implanted 4H-SiC Layers by Four Point Probe and Scanning Capacitance Microscopy

We studied the evolution of the electrical activation with annealing temperature and time in 4H-SiC implanted with Al ions at room temperature (RT). An accurate comparison between the electrical activation data obtained by FPP and SCM was carried out. The dependence of the electrically active profiles on annealing time was studied during isothermal (Tann=1600 °C) annealings for times ranging from 0 (spike anneal) to 30 min. By performing isochronal (t=30 min) processes at temperatures from 1550 to 1650 °C, the effect of the annealing temperature on the net doping concentration profiles was studied. Moreover, the activation energy (6.30.3 eV) associated to the process was extracted from the Arrhenius plot of the net active dose. Finally, the effect of the different thermal budgets on the roughening of the Al implanted 4H-SiC surface was also investigated in details by atomic force microscopy.

Effect of Shallow n-Doping on Field Effect Mobility in p-Doped Channels of 4H-SiC MOS Field Effect Transistors

A high inversion channel mobility is a key parameter of normally off Silicon-Carbide MOS field effect power transistors. The mobility is limited by scattering centers at the interface between the semiconductor and the gate-oxide. In this work we investigate the mobility of lateral normally-off MOSFETs with different p-doping concentrations in the channel. Additionally the effect of a shallow counter n-doping at the interface on the mobility was determined and, finally, the properties of interface traps with the charge pumping method were examined. A lower p-doping in the cannel reduces the threshold voltage and increases the mobility simultaneously. A shallow counter n-doping shows a similar effect, but differences in the behavior of the charge pumping current can be observed, indicating that the nitrogen has a significant effect on the electrical properties of the interface, too.

Structural Characterization of Graphene Grown by Thermal Decomposition of Off-Axis 4H-SiC (0001)

We present a nanoscale morphological and structural characterization of few layers of graphene grown by thermal decomposition of off-axis 4H-SiC (0001). A comparison between transmission electron microscopy (TEM) in cross-section and in plan view allows to fully exploit the potentialities of TEM. Such a comparison was used to get information on the number of graphene layers as well as on the rotational order between the layers and with respect to the substrate. Some peculiar structures observed by TEM (wrinkles) could only be systematically measured by atomic force microscopy (AFM). In particular, the density and the height of the wrinkles in the few layers of graphene was investigated.

Impurity conduction in silicon carbide

We report on admittance spectroscopy (AS) investigations taken on aluminum (Al)- doped 6H-SiC crystals at low temperatures. Admittance spectra taken on Schottky contacts of highly doped samples (NA ≥ 7.2×1017 cm-3) reveal two series of conductance peaks, which cause two different slopes of the Arrhenius plot. The steep slope is attributed to the Al acceptor, while the flatter one - obtained from the low temperature peaks - is attributed to the activation energy ε3 of nearest neighbor hopping. We propose a model, which explains the unexpected sharpness of the low temperature conductance peaks and the disappearance of these peaks for low acceptor concentrations. The model is verified by simulation, and the AS results are compared with corresponding results obtained from resistivity measurements taken on 4H- and the identical 6HSiC samples.

Impact of Post-Trench Processing on the Electrical Characteristics of 4H-SiC Trench-MOS Structures with Thick Top and Bottom Oxides

This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 °C are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO2) both at the wafer surface (‘top’) and in the bottom of the trenches (‘bottom’) in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 °C and 1550 °C yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO2 gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 °C confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm² have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.

Influence of Annealing, Oxidation and Doping on Conduction-Band near Interface Traps in 4H-SiC Characterized by Low Temperature Conductance Measurements

Current power MOSFET devices on Silicon Carbide show a limited inversion channel mobility, which can be a result of the expected very high density of interface states near the conduction band . In the current work, the effect of the post implantation annealing temperature, the thermal oxidation and the nitrogen doping of the n-epi layer on the density of these interface traps is investigated using capacity-conductance measurements. Instead of the usage of very high frequencies as used in , in this investigation the measurements were performed in liquid nitrogen to decrease the recharging times of the interface traps.Due to the different processing the samples showed a wide spreading of the inversion channel mobility. The conductance measurements show a characteristic peak caused by the conduction band near interface traps especially for the low temperature measurements. But these traps could not be correlated to the mobility. Instead, a correlation to the nitrogen doping of the epi layer could be observed.

Influence of Post-Implantation Annealing Temperature on MOSFET Performance and Oxide Reliability

In the present work, we studied the influence of the post-implantation annealing temperature on the performance and oxide reliability of lateral 4H-SiC MOSFETs. The maximum field effect mobility of the MOSFETs at 25°C decreases from 22.4cm2/Vs to 17.2cm2/Vs by increasing annealing temperature from 1600°C to 1800°C. Respectively, the measured meantime to failure is about one order of magnitude higher for the 1700°C annealed sample at an applied field of 8.5MV/cm compared to the 1600°C and 1800°C annealed samples.

Temperature Dependent Structural Evolution of Graphene Layers on 4H-SiC(0001)

In this study we examined the structural evolution of graphene grown on 8° off-axis 4H-SiC(0001) substrates at temperatures from 1600°C to 1700°C in Ar ambient. Morphological transformation of SiC substrate after annealing was examined by Tapping Mode Atomic Force Microscopy. Moreover, by etching-out graphene layers from graphitized SiC substrates in selective trenches we determined the number of graphene layers. Numbers of graphene layers were then independently confirmed by Transmission Electron Microscopy imaging.