Antoni Portero

Mixed SW/SystemC SoC Emulation Framework

Developing HW modules for standard platforms like PCs or embedded devices requires a complete system emulator availability to detect and fix bugs on developed HW, Operating Systems (OS) drivers and applications. This paper presents a set of plug-ins to an open-source CPU emulator that enables mixed simulations between platforms emulators and hardware (HW) modules described in SystemC. In this paper three plugins for QEMU are described: one for connecting TLM SystemC modules to any bus QEMU emulates, one for connecting SystemC to PCI bus for PC based platform and one plug-in for connecting SystemC to AMBA bus for ARM platforms. With this framework, it is possible to develop OS drivers at the same time HW is developed and final application tested running in this virtual platform.

Simulating a Multi-core x8664 Architecture with Hardware ISA Extension Supporting a Data-Flow Execution Model

The trend to develop increasingly more intelligent systems leads directly to a considerable demand for more and more computational power. Programming models that aid to exploit the application parallelism with current multi-core systems exist but with limitations. From this perspective, new execution models are arising to surpass limitations to scale up the number of processing elements, while dedicated hardware can help the scheduling of the threads in many-core systems. This paper depicts a data-flow based execution model that exposes to the multi-core x8664 architecture up to millions of fine-grain threads. We propose to augment the existing architecture with a hardware thread scheduling unit. The functionality of this unit is exposed by means of four dedicated instructions. Results with a pure data-flow application (i.e., Recursive Fibonacci) show that the hardware scheduling unit can load the computing cores (up to 32 in our tests) in a more efficient way than run-time managed threads generated by programming models (e.g., OpenMP and Cilk). Further, our solution shows better scaling and smaller saturation when the number of workers increases.

Methodology for Energy-Flexibility Space Exploration and Mapping of Multimedia Applications to Single-Processor Platform Styles

Embedded multimedia devices are now a common element of our environment, such as mp3 players, handheld devices, and so on. Choosing the right main processing element is a key issue for the success of these devices, and their consumption, performance, retargetability, and development time are some of the elements that need to be analyzed and well-balanced. In this paper, we map the same multimedia application (MPEG-4 main profile) into various target platforms generally used in the embedded area. The design flow of our work starts with a single MPEG-4 encoder description which is later refined and optimized to be implemented on different platforms: an embedded platform formed by a high performance digital signal processor and an embedded processor, an application specific instruction processor, a specific hardware implemented in a field-programmable gate array for accelerating the data-flow part of the system with a soft-core for the control part, and an application specific integrated circuit. The main contribution of this paper is to illustrate a methodology that can be generalized to different data dominant applications. This paper describes a new methodology to obtain near optimal implementation from concept to silicon for all platforms and it can be extended to any hybrid HW/SW multimedia platform. We evaluate the different transformations of each platform to arrive at an optimal implementation. These higher level transformations allow achieving better results than using more precise efforts in mapping the design in the physical level. This methodology can be extended to any data dominant application.

System and Application Scenarios for Disaster Management Processes, the Rainfall-Runoff Model Case Study

In the future, the silicon technology will continue to reduce following the Moore’s law. Device variability is going to increase due to a loss in controllability during silicon chip fabrication. Then, the mean time between failures is also going to decrease. The current methodologies based on error detection and thread re-execution (roll back) can not be enough, when the number of errors increases and arrives to a specific threshold. This dynamic scenario can be very negative if we are executing programs in HPC systems where a correct, accurate and time constrained solution is expected. The objective of this paper is to describe and analyse the needs and constraints of different applications studied in disaster management processes. These applications fall mainly in the domains of the High Performance Computing (HPC). Even if this domain can have differences in terms of computation needs, system form factor and power consumption, it nevertheless shares some commonalities.

Harnessing Performance Variability: A HPC-Oriented Application Scenario

The technology scaling towards the 10nm of the silicon manufacturing, is going to introduce variability challenges, mainly due to the growing susceptibility to thermal hot-spots and time-dependent variations (aging) in the silicon chip. The consequences are two-fold: a) unpredictable performance, b) unreliable computing resources. The goal of the HARPA project is to enable next-generation embedded and high-performance heterogeneous many-core processors to effectively address this issues, through a cross-layer approach, involving several component of the system stack. Each component acts at different levels and time granularity. This paper focus on one of the components of the HARPA stack, the HARPA-OS, showing early results of a first integration step of the HARPA approach in a real High-Performance Computing (HPC) application scenario.

NoC Design of a Video Encoder in a Multiprocessor System on Chip Solution

Future multiprocessor system-on-a-chip (MPSoC) will need high performance and low power requirements due to user demand and limited battery life. In this paper, we take advantage of the architecture flexibility allowed by Network-on-Chip (NoC) to build a parameterizable MPEG Compressor. MPEG compressor System has been developed in synthetizable behavioural SystemC, as a flexible system divided in different tiles. Each tile can be configured as a functional block with different performance parameters in terms of power/speed/area. NoC design implements a 2D mesh with a parameterizable router implemented in high level TLM SystemC. A QoS module takes decisions on packet routing depending on macro-block encoded data (corresponding to I, P and B frames) in real time in terms of power or performance requirements.

HARPA: Solutions for dependable performance under physically induced performance variability

Transistor miniaturization, combined with the dawn of novel switching semiconductor structures, calls for careful examination of the variability and aging of the computer fabric. Time-zero and time-dependent phenomena need to be carefully considered so that the dependability of digital systems can be guaranteed. Already, architectures contain many mechanisms that detect and correct physically induced reliability violations. In many cases, guarantees on functional correctness come at a quantifiable performance cost. The current paper discusses the FP7-612069-HARPA project of the European Commission and its approach towards dependable performance. This project provides solutions for performance variability mitigation, under the run time presence of fabric variability/aging and built-in reliability, availability and serviceability (RAS) techniques. In this paper, we briefly present and discuss modeling and mitigation techniques developed within HARPA, covering many abstractions of digital system design: from the transistor to the application layer.

Software defined Network-on-Chip for scalable CMPs

Moving from Petascale to Exascale computing necessitates optimizing the micro-architectural to increase the performance/power ratio of multicores (e.g., FLOPS/W). Future manycore processors will contain thousands of low-powered processing elements (kilo-core Chip Multi-Processors - CMPs) to support the execution of a large number of concurrent threads. While data-driven Program eXecution Models (PXMs) are gaining popularity due to the support they provide for thread communication, frequent data exchange among many concurrent threads puts stress on the underlying interconnect subsystem. This results in hotspots and high latency for data packet delivering. As a solution, we propose a scalable Software Defined Network-on-Chip (SDNoC) architecture for future manycore processors. Our design tries to merge the benefits of ring-based NoCs (i.e., performance, energy efficiency) with those brought by dynamic reconfiguration (i.e., adaptation, fault tolerance) while keeping the hard-wired topology (2D-mesh) fixed. To potentially accommodate different application and communication requirements, our interconnect allows mapping different types of topologies (virtual topologies). To allow the software layer to control and monitor the NoC subsystem, few customized instructions supporting a data-driven PXM are added to the core ISA. In experiments, we compared our lightweight reconfigurable architecture to a conventional 2D-mesh interconnection subsystem. Results show that our model allows savings of 39.4% of the chip area and up to 72.4% of the consumed power.

Dynamic computing resource allocation in online flood monitoring and prediction

This paper presents tools and methodologies for dynamic allocation of high performance computing resources during operation of the Floreon+ online flood monitoring and prediction system. The resource allocation is done throughout the execution of supported simulations to meet the required service quality levels for system operation. It also ensures flexible reactions to changing weather and flood situations, as it is not economically feasible to operate online flood monitoring systems in the full performance mode during non-flood seasons. Different service quality levels are therefore described for different flooding scenarios, and the runtime manager controls them by allocating only minimal resources currently expected to meet the deadlines. Finally, an experiment covering all presented aspects of computing resource allocation in rainfall-runoff and Monte Carlo uncertainty simulation is performed for the area of the Moravian-Silesian region in the Czech Republic.

Adopting New Competences Experience in the Face of Engineering Learning

The so-called Bologna process has opened a stage of deep changes in the university teaching methods in most European countries. Our work, which is focused on Spanish university reality, describes the changes that an engineering student must face in his/her learning habits as well as the new education methodologies followed by teaching staff to motivate and promote these changes. Some of these methodologies are oriented to create/reinforce a learning culture in the student and favor an intensive use of e-learning. Both elements play an important role as basis of the lifelong learning