Radim Vavrik

Harnessing Performance Variability: A HPC-Oriented Application Scenario

The technology scaling towards the 10nm of the silicon manufacturing, is going to introduce variability challenges, mainly due to the growing susceptibility to thermal hot-spots and time-dependent variations (aging) in the silicon chip. The consequences are two-fold: a) unpredictable performance, b) unreliable computing resources. The goal of the HARPA project is to enable next-generation embedded and high-performance heterogeneous many-core processors to effectively address this issues, through a cross-layer approach, involving several component of the system stack. Each component acts at different levels and time granularity. This paper focus on one of the components of the HARPA stack, the HARPA-OS, showing early results of a first integration step of the HARPA approach in a real High-Performance Computing (HPC) application scenario.

HARPA: Solutions for dependable performance under physically induced performance variability

Transistor miniaturization, combined with the dawn of novel switching semiconductor structures, calls for careful examination of the variability and aging of the computer fabric. Time-zero and time-dependent phenomena need to be carefully considered so that the dependability of digital systems can be guaranteed. Already, architectures contain many mechanisms that detect and correct physically induced reliability violations. In many cases, guarantees on functional correctness come at a quantifiable performance cost. The current paper discusses the FP7-612069-HARPA project of the European Commission and its approach towards dependable performance. This project provides solutions for performance variability mitigation, under the run time presence of fabric variability/aging and built-in reliability, availability and serviceability (RAS) techniques. In this paper, we briefly present and discuss modeling and mitigation techniques developed within HARPA, covering many abstractions of digital system design: from the transistor to the application layer.

Flood Prediction Model Simulation With Heterogeneous Trade-Offs In High Performance Computing Framework.

In this paper, we propose a safety-critical system with a run-time resource management that is used to operate an application for flood monitoring and prediction. This application can run with different Quality of Service (QoS) levels depending on the current hydrometeorological situation. The system operation can follow two main scenarios standard or emergency operation. The standard operation is active when no disaster occurs, but the system still executes shortterm prediction simulations and monitors the state of the river discharge and precipitation intensity. Emergency operation is active when some emergency situation is detected or predicted by the simulations. The resource allocation can either be used for decreasing power consumption and minimizing needed resources in standard operation, or for increasing the precision and decreasing response times in emergency operation. This paper shows that it is possible to describe different optimal points at design time and use them to adapt to the current quality of service requirements during run-time.

Automatic calibration of rainfall-runoff models and its parallelization strategies

For successful decision making in disaster management it is necessary to have very accurate information about disaster phenomena and its potential developmentin time. Rainfall-runoff simulations are an integral part of flood warning and decision making processes. To increase their accuracy, it is crucial to periodically updatetheir parametersin a calibration process.Since calibration is very time consuming process an HPC facility is convenient tool for its speed-up. However, required speed-up can be achieved only avoiding any human-computer interaction in so-called automatic calibration.In order to compare possibilities and efficiency of the automatic calibration, three different fully automatic parallel implementationstrategies were created and tested with our in-house rainfall-runoff model.

Dynamic computing resource allocation in online flood monitoring and prediction

This paper presents tools and methodologies for dynamic allocation of high performance computing resources during operation of the Floreon+ online flood monitoring and prediction system. The resource allocation is done throughout the execution of supported simulations to meet the required service quality levels for system operation. It also ensures flexible reactions to changing weather and flood situations, as it is not economically feasible to operate online flood monitoring systems in the full performance mode during non-flood seasons. Different service quality levels are therefore described for different flooding scenarios, and the runtime manager controls them by allocating only minimal resources currently expected to meet the deadlines. Finally, an experiment covering all presented aspects of computing resource allocation in rainfall-runoff and Monte Carlo uncertainty simulation is performed for the area of the Moravian-Silesian region in the Czech Republic.

Using an adaptive and time predictable runtime system for power-aware HPC-oriented applications

An increasing number of High-Performance Applications demand some form of time predictability, in particular in scenarios where correctness depends on both performance and timing requirements, and the failure to meet either of them is critical. Consequently, a more predictable HPC system is required, particularly for an emerging class of adaptive real-time HPC applications. Here we present our runtime approach which produces the results in the predictable time with the minimized allocation of hardware resources. The paper describes the advantages in terms of execution time reliability and the trade-offs regarding power/energy consumption and temperature of the system compared with the current GNU/Linux governors.

Framework for scheduling and resource management in time-constrained HPC application

The silicon technology continues reducing scale following the Moore’s law. Device variability increases due to a lost in controllability during silicon chip fabrication. The current methodologies based on error detection and thread re-execution (roll back) cannot be enough, when the number of errors increase and arrive to a threshold. This dynamic scenario can be very negative if we are executing programs in HPC systems where a correct, accurate and time constraints solution is expected. The objective of the paper is to show preliminary results of Barbeque OpenSource Project (BOSP) and its potential use in HPC systems.

Floreon+ Modules: A Real-World HARPA Application in the High-End HPC System Domain

This chapter is centered around uncertainty computation with on-demand resource allocation for run-off prediction in a High-Performance Computer environment. Our research stands on a runtime operating system that automatically adapts resource allocation with the computation to provide precise outcomes before the time deadline. In our case, input data comes from several gauging stations, and when newly updated data arrives, models must be re-executed to provide accurate results immediately. Since the models run continuously (24/7), their computational demand is different during various hydrological events (e.g. periods with heavy rain and without any rain) and therefore computational resources have to be balanced according to the event severity. Although these kinds of models should run constantly, they are very computationally demanding during discrete periods of time, for example in the case of heavy rain. Then, the accuracy of the results must be as close as possible to reality. The work relies on the HARPA runtime resource manager that adapts resource allocation to the runtime-variable performance demand of applications. The resource assignment is temperature-aware: the application execution is dynamically migrated to the coolest cores, and this has a positive impact on the system reliability.

Evaluating System-Level Monitors and Knobs on Real Hardware

This chapter evaluates and defines a methodology for the oracle selection of the monitors and knobs to use to configure an HPC system running a scientific application while satisfying the application’s requirements and not violating any system constraints. This methodology relies on a heuristic correlation analysis between requirements, monitors, and knobs to determine the minimum subset of monitors to observe and knobs to explore to determine the optimal system configuration for the HPC application. The setup under examination is the Floreon+ application, along with IT4I’s cluster. At the end of this analysis, the eleven-dimensional was reduced to a three-dimensional space for monitors and a six-dimensional space to a three-dimensional space for knobs. This reduction shows the potential and highlights the need for a realistic methodology to help identify such a minimum set of monitors and knobs. Additionally, a characterization of the application is provided by showing that Floreon+ performance requirements are satisfied with a CPU frequency lower than the servers nominal CPU frequency.

The HARPA Approach to Ensure Dependable Performance

The goal of the HARPA solution is to overcome the performance variability (PV) by enabling next-generation embedded and high-performance platforms using heterogeneous many-core processors to provide cost-effectively dependable performance: the correct functionality and (where needed) timing guarantees throughout the expected lifetime of a platform. This must be accomplished in the presence of cycle-by-cycle performance variability due to time-dependent variations in silicon devices and wires under thermal, power, and energy constraints. The common challenge for both embedded and high-performance systems is to harness the unsustainable increases in design and operational margins and yet provide dependable performance. For example, resources that are statically determined based on worst-case execution time for real-time applications or lower clock frequency to satisfy excessive timing margins in high-performance processors.