Antonio Artes

A Configurable and Low-Power Mixed Signal SoC for Portable ECG Monitoring Applications

This paper describes a mixed-signal ECG System-on-Chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel electrode-tissue-impedance (ETI) measurement with high signal quality. This can be used to evaluate the quality of the ECG measurement and to filter motion artifacts. A custom digital signal processor consisting of 4-way SIMD processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. A built-in 12-bit analog-to-digital converter (ADC) is capable of adaptive sampling achieving a compression ratio of up to 7, and loop buffer integration reduces the power consumption for on-chip memory access. The SoC is implemented in 0.18 μm CMOS process and consumes 32 μW from a 1.2 V while heart beat detection application is running, and integrated in a wireless ECG monitoring system with Bluetooth protocol. Thanks to the ECG SoC, the overall system power consumption can be reduced significantly.

Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems

Instruction memory organisations have been pointed out as one of the major sources of energy consumption in embedded systems. As embedded systems are characterised by restrictive resources and a low-energy budget, any enhancement that is introduced into this component of the system will allow embedded designers not only to decrease the total energy consumption, but also to have a better distribution of the energy budget throughout the whole system. The work that is presented in this paper provides a synthesis on the low-energy techniques that are used in instruction memory organisations, outlining their comparative advantages, drawbacks, and trade-offs. Apart from giving the reader a first grasp on the fundamental characteristics and design constraints of various types of instruction memory organisations, the architectural classification that is presented in this paper has the advantage of clearly exhibiting lesser explored techniques, and hence providing hints for future research on instructions memory organisations that are used in embedded systems.

Power Impact of Loop Buffer Schemes for Biomedical Wireless Sensor Nodes

Instruction memory organisations are pointed out as one of the major sources of energy consumption in embedded systems. As these systems are characterised by restrictive resources and a low-energy budget, any enhancement in this component allows not only to decrease the energy consumption but also to have a better distribution of the energy budget throughout the system. Loop buffering is an effective scheme to reduce energy consumption in instruction memory organisations. In this paper, the loop buffer concept is applied in real-life embedded applications that are widely used in biomedical Wireless Sensor Nodes, to show which scheme of loop buffer is more suitable for applications with certain behaviour. Post-layout simulations demonstrate that a trade-off exists between the complexity of the loop buffer architecture and the energy savings of utilising it. Therefore, the use of loop buffer architectures in order to optimise the instruction memory organisation from the energy efficiency point of view should be evaluated carefully, taking into account two factors: (1) the percentage of the execution time of the application that is related to the execution of the loops, and (2) the distribution of the execution time percentage over each one of the loops that form the application.

Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications

Instruction memory organization is pointed out as one of the major sources of energy consumption in embedded systems. As embedded systems are characterized by restrictive resources and low energy budget, any enhancement in this component allows not only to decrease the total energy consumption, but also to have a better distribution of the energy budget throughout the system. This paper presents a self-tuning banked loop buffer architecture, which is based on a run-time loop buffer controller that optimizes both the dynamic and leakage energy consumption of the instruction memory organization. Results show that using banking in loop buffer architectures leads to higher reduction in the total energy consumption of the instruction memory organization if the tuning approach is applied sparingly. Based on post-layout simulations, our approach improves the total energy consumption by average of 20% in comparison with a loop buffer architecture based on a single monolithic memory, and more than 90% in comparison with instruction memory organizations without loop buffer architectures.

IMOSIM: Exploration tool for Instruction Memory Organisations based on accurate cycle-level energy modelling

The energy budget of embedded instruction-set processor platforms is significantly affected by the Instruction Memory Organisation. Due to the fact that the design space of the enhancements for reducing the energy consumption of this component is huge, this paper proposes a high-level energy estimation tool that, for a given application and compiler, allows the exploration not only of architectural and compiler configurations, but also of code transformations that are related to the Instruction Memory Organisation. The proposed tool, with a mean error of 3.95%, achieves reductions in time and effort to explore the design space of the Instruction Memory Organisation.

Energy impact in the design space exploration of loop buffer schemes in embedded systems

The reduction of the energy consumption in the domain of the embedded systems is becoming the most important design goal due to the increasing use of battery powered consumer devices. Previous research has pointed out the instruction memory organisation as one of the major sources of energy consumption of the embedded systems. Due to this fact, the introduction of any enhancement in this component of the system becomes crucial in order to decrease this energy bottleneck. The purpose of this paper is to present a highlevel energy analysis of the loop buffer schemes that exist in the embedded systems. The crucial energy analysis that is presented in this paper not only proposes a method to evaluate different loop buffer schemes for a certain application, but also guides embedded systems designers to make the correct decision in the trade-offs that exist between the energy budget, the required performance, and the area cost of the embedded system. Experimental results used in this analysis show that, the search of energy savings (up to 76%) has to take into account the performance penalty, the area cost, and the impact of the implementation technology in order to choose the most suitable enhancement that has to be introduced in the instruction memory organisation from the point of view of the energy consumption.

[2010] Energy Efficiency Using Loop Buffer based Instruction Memory Organizations

Energy consumption in embedded systems is strongly dominated by instruction memory organizations. Based on this, any architectural enhancement introduced in this component will produce a significant reduction of the total energy bud-get of the system. Loop buffering is an effective scheme to reduce the energy consumption of the instruction memory organization.In this paper, a novel classification of architectural enhancements based on the use of loop buffer concept is presented. Using this classification, an energy design space exploration is performed to show the impact in the energy consumption on different application scenarios. From gate-level simulations, the energy analysis demonstrates that the instruction level parallelism of the system brings not only improvements in performance, but also improvements in the energy consumption of the system.The increase in instruction level parallelism makes easy the adaptation of the sizes of the loop buffers to the sizes of the loops that form the application, because gives more freedom to combine the execution of the loops that form the application.