Antonio Cerdeira

Double-gate junctionless transistor model including short-channel effects

This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), such as increase of the channel potential due to drain bias, carrier velocity saturation and mobility degradation due to vertical and longitudinal electric fields, are included in a previous model developed for long-channel double-gate JLTs. To validate the model, an analysis is made by using three-dimensional numerical simulations performed in a Sentaurus Device Simulator from Synopsys. Different doping concentrations, channel widths and channel lengths are considered in this work. Besides that, the series resistance influence is numerically included and validated for a wide range of source and drain extensions. In order to check if the SCEs are appropriately described, besides drain current, transconductance and output conductance characteristics, the following parameters are analyzed to demonstrate the good agreement between model and simulation and the SCEs occurrence in this technology: threshold voltage (VTH), subthreshold slope (S) and drain induced barrier lowering.

Drain current model for short-channel triple gate junctionless nanowire transistors

Abstract This work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration of a single expression that physically describes the junctionless charge density in both accumulation and depletion regimes of operation, leading to a continuous model in all operational regions. The triple gate structure is modeled from an evolution of a previous model designed for double gate junctionless nanowire transistors (2G JNT). Improvements concerning the capacitance coupling, the internal potential changing while reducing the fin height in nanowire transistors and higher immunity to short-channel effects (SCE) are considered. The model validation is performed through both tridimensional numerical simulation and experimental measurements for long and short-channel devices. Through simulated results, it is verified the agreement of the modeled curves for junctionless transistors with different values of fin height. Comparison between the proposed model and experimental data is performed for 3G JNT advanced structures with channel length down to 15xa0nm and fin height of 8xa0nm. Results for 3G JNTs with different values of doping concentration and channel width are also displayed showing a good agreement as well. Moreover, 3G JNT performance is also analyzed and compared in the studied structures by extracting the threshold voltage ( V TH ), subthreshold slope ( S ), DIBL and model parameters.

Analysis of the Performance of an Inverter Circuit: Varying the Thickness of the Active Layer in Polymer Thin Film Transistors with Circuit Simulation

In this paper, we study, through simulation, the effects on the behavior of an inverter circuit when the active layer thickness of the polymer thin film transistor design is modified. A previously developed compact model for polymer transistors was implemented in standardized hardware description language. We validate results with measured characteristics of transistors fabricated with a poly(methyl methacrylate) layer on top of a poly(3-hexylthiophene-2,5-diyl). This analysis indicates that decreasing the thickness of the active layer can increase the output voltage swing and hence the noise margin in digital circuits. Higher noise margin and larger gain were found for inverters with active layer thicknesses less than 40 nm.

Optimised design of an organic thin-film transistor amplifier using the gm/ID methodology

Most of the applications of circuits that are currently in existence use mainly digital circuits. However, interfacing with the external world is a task that can be only accomplished by analog circuits. Thus, to obtain a functional system, some attention must be paid to them, especially when using organic thin-film transistors. In this case, some new issues arise that are very different from those in the digital world. Analog circuits pose a special problem to analog designers. Owing to their low mobilities, they present very low gains, and biasing them in the right point becomes a critical point. Another critical aspect is the high parameter dispersion, which makes analog designs quite complex. In this study, we will try to present a similar strategy, adapted to the specific case of organic TFTs.

Effects of impurity concentration, hydrogen plasma process and crystallization temperature on poly-crystalline films obtained from PECVD a-Si:H layers

Abstract In this work we report the effects of impurity concentration and crystallization temperature on the crystalline orientation and final layer resistivity of poly-crystalline films obtained from a-Si:H layers deposited by PECVD at 225 °C followed by a hydrogen plasma process in the same PECVD equipment in which they are deposited. Films were characterized electrically, by X-ray diffractometry and by transmission electron microscopy. Crystallized films were used to fabricate poly-Si TFTs.

Verilog-A implementation of a double-gate junctionless compact model for DC circuit simulations

A physically based model of the double-gate juntionless transistor which is capable of describing accumulation and depletion regions is implemented in Verilog-A in order to perform DC circuit simulations. Analytical description of the difference of potentials between the center and the surface of the silicon layer allows the determination of the mobile charges. Furthermore, mobility degradation, series resistance, as well as threshold voltage roll-off, drain saturation voltage, channel shortening and velocity saturation are also considered. In order to provide this model to all of the community, the implementation of this model is performed in Ngspice, which is a free circuit simulation with an ADMS interface to integrate Verilog-A models. Validation of the model implementation is done through 2D numerical simulations of transistors with and silicon channel length and 1 × 1019 or doping concentration of the silicon layer with 10 and silicon thickness. Good agreement between the numerical simulated behavior and model implementation is obtained, where only eight model parameters are used.

Parasitic Gate Resistance Impact on Triple-Gate FinFET CMOS Inverter

In this paper, based on a full intrinsic-extrinsic model for symmetric doped double-gate MOSFET, we analyze the impact of FinFET gate resistance over the inverter and ring oscillator performance. It is shown that, when the total number of fins remains constant, the propagation delay can be improved thanks to the multifinger configuration that translates into the gate resistance reduction. Furthermore, the fin spacing in addition to source/drain fin extension reduction are of primary importance to improve the digital circuit performance.