Eugeni García-Moreno

Floating Gate CMOS Dosimeter With Frequency Output

This paper presents a gamma radiation dosimeter based on a floating gate sensor. The sensor is coupled with a signal processing circuitry, which furnishes a square wave output signal, the frequency of which depends on the total dose. Like any other floating gate dosimeter, it exhibits zero bias operation and reprogramming capabilities. The dosimeter has been designed in a standard 0.6 m CMOS technology. The whole dosimeter occupies a silicon area of 450 m250 m. The initial sensitivity to a radiation dose is Hz/rad, and to temperature and supply voltage is kHz/°C and 0.067 kHz/mV, respectively. The lowest detectable dose is less than 1 rad.

Temperature Compensated Floating Gate MOS Radiation Sensor With Current Output

This paper presents an improved version of our previous gamma radiation sensor based on a floating gate MOSFET whose output current is changed by the total ionizing dose. Both versions exhibit zero bias operation and reprogramming capabilities. They have been designed in a standard CMOS technology, require little silicon area, and exhibit low power consumption. Sensitivity to radiation dose is -11.4 μA/krad, dose range over 3.6 krad, and lowest detectable dose lower than 2 rad. The new version features much higher linearity and supply voltage rejection and much lower sensitivity to ambient temperature.

Application of Predictive Oscillation-Based Test to a CMOS OpAmp

A predictive oscillation-based test (POBT) strategy, combined with supply current monitoring, is proposed as an alternative to the specification-based test of analog circuits. According to our simulation results, the combination of both techniques is excellent in predicting the main performance parameters of a CMOS operational amplifier (OpAmp) (dc gain, bandwidth, and slew rate) from test observables such as oscillation frequency and variations on the supply current. Considering tolerances in the fabrication process, a set of mapping functions has been found by circuit simulation, giving correlation coefficients higher than 0.999 and RMS prediction errors below 1.5%. A set of 19 fabricated circuits has been measured in both normal and test modes. The correlation between performance parameters and test observables, which are both measured, gives RMS errors of 0.65% for the dc gain, 11.30% for the bandwidth, and 4.12% for the slew rate.

A new procedure to extract the threshold voltage of MOSFETs using noise-reduction techniques

Abstract A new way to extract the threshold voltage of MOSFET is presented. It combines the well known extraction method based on determining the maximum of the second derivative of I D with respect to V GS for V DS approaching zero, with digital signal processing techniques to increase the signal/noise ratio. The derivatives are calculated on the Fourier transform space and a low-pass filter is used to smooth the function before taking the inverse transform. This procedure combines the advantage of being a standard method based on a physical property, with a noise immunity comparable to the most recent extraction methods, without requiring a costly computing effort. The results are compared with other methods using experimental data from 0.7 and 0.07 μm bulk CMOS technologies.

Predictive test strategy for CMOS RF mixers

In this paper, we present two built-in self-test strategies for the down-converter stage in a GSM receiver. These strategies are based on the prediction of its performance parameters from measurements in test mode. By reusing some receiver blocks as part of the test set-up, the circuitry overhead is kept small. The first strategy uses the local oscillator (LO) signal as the only test stimuli. The second strategy uses additional test circuitry, a generator, and an auxiliary mixer. Prediction accuracies are similar in both strategies, but the test observables in the second one are easier to be obtained.

Experimental results on BIC sensors for transient current testing

In this work experimental results on a built-in current sensor for dynamic current testing, i(t), based on integration concepts are presented. The experimental validation proposed in this work is done through a VLSI CMOS circuit implemented in a 0.7 μm technology. Different experiences have been developed analyzing the detectability of several kind of defects through this technique. The encouraging results obtained present this technique as an attractive complement to boolean and I testing.

Predictive Oscillation Based Test of CMOS circuits

Two different CMOS circuits has been used to check the predictive oscillation based test (POBT) approach, combined with supply current monitoring technique. These circuits are a two stage op amp and a biquad filter composed by two transconductance amplifiers (OTA). The combination of both techniques has given excellent results in predicting the main performance parameters of the circuits as DC gain, bandwidth or slew-rate in the opamp and cut-off frequency, quality factor or rise time in the filter. When considering tolerances in the fabrication process, correlation coefficients higher than 0.998 for the opamp and 0.95 for the biquad filter have been found. These good results open the door to a new built in test strategy, and alleviates the need of more complex techniques to enhance the efficiency of the POBT requiring sophisticated acquisition systems

Exploring ReRAM-based memristors in the charge-flux domain, a modeling approach

We analyzed ReRAM-based memristors by using the charge-flux relations instead of the traditional current-voltage approach. We used simulated and experimental data to develop a circuit model. Simulations of devices with different conductive filament sizes were employed to fit a 3-parameter model, later on the relations between the model parameters were characterized in-depth. Finally, we used the model to estimate the experimental conductive filament radius distribution using 3000 reset cycles.

Optimised design of an organic thin-film transistor amplifier using the gm/ID methodology

Most of the applications of circuits that are currently in existence use mainly digital circuits. However, interfacing with the external world is a task that can be only accomplished by analog circuits. Thus, to obtain a functional system, some attention must be paid to them, especially when using organic thin-film transistors. In this case, some new issues arise that are very different from those in the digital world. Analog circuits pose a special problem to analog designers. Owing to their low mobilities, they present very low gains, and biasing them in the right point becomes a critical point. Another critical aspect is the high parameter dispersion, which makes analog designs quite complex. In this study, we will try to present a similar strategy, adapted to the specific case of organic TFTs.

An analytical energy model for the reset transition in unipolar resistive-switching RAMs

In this paper we develop and test an analytical model for the total energy dissipation during the reset transition of an unipolar ReRAM device. To do so, we have considered the ReRAM as a memristor, and we have used a memristor model in the Charge-Flux space, instead of the usual current-voltage variables. The used model is very simple, with only three parameters, and provides accurate results. It also allows developing simple expressions for the power and energy consumption. We consider the case of a ramp input signal, and we compare the predictions of our 3-parameters model with experimental results, with an average error below 1%. We also present the compact expressions for the case of a ReRAM undergoing a reset transition with a pulsed input.