Antonio F. Díaz

Multiobjective evolutionary optimization of the size, shape, and position parameters of radial basis function networks for function approximation

This paper presents a multiobjective evolutionary algorithm to optimize radial basis function neural networks (RBFNNs) in order to approach target functions from a set of input-output pairs. The procedure allows the application of heuristics to improve the solution of the problem at hand by including some new genetic operators in the evolutionary process. These new operators are based on two well-known matrix transformations: singular value decomposition (SVD) and orthogonal least squares (OLS), which have been used to define new mutation operators that produce local or global modifications in the radial basis functions (RBFs) of the networks (the individuals in the population in the evolutionary procedure). After analyzing the efficiency of the different operators, we have shown that the global mutation operators yield an improved procedure to adjust the parameters of the RBFNNs.

PSFGA: a parallel genetic algorithm for multiobjective optimization

This paper presents the parallel single front genetic algorithm (PSFGA), a parallel Pareto-based algorithm for multiobjective optimization problems based on an evolutionary procedure. In this procedure, a population of solutions is sorted with respect to the values of the objective functions and partitioned into subpopulations which are distributed among the processors. Each processor applies a sequential multiobjective genetic algorithm that we have devised (called single front genetic algorithm, SFGA) to its subpopulation. Experimental results are provided comparing PSFGA with previously proposed multiobjective evolutionary algorithms.

Short-term prediction of chaotic time series by using RBF network with regression weights.

We propose a framework for constructing and training a radial basis function (RBF) neural network. The structure of the gaussian functions is modified using a pseudo-gaussian function (PG) in which two scaling parameters sigma are introduced, which eliminates the symmetry restriction and provides the neurons in the hidden layer with greater flexibility with respect to function approximation. We propose a modified PG-BF (pseudo-gaussian basis function) network in which the regression weights are used to replace the constant weights in the output layer. For this purpose, a sequential learning algorithm is presented to adapt the structure of the network, in which it is possible to create a new hidden unit and also to detect and remove inactive units. A salient feature of the network systems is that the method used for calculating the overall output is the weighted average of the output associated with each receptive field. The superior performance of the proposed PG-BF system over the standard RBF are illustrated using the problem of short-term prediction of chaotic time series.

Annealing-based heuristics and genetic algorithms for circuit partitioning in parallel test generation

Abstract In this paper simulated annealing and genetic algorithms are applied to the graph partitioning problem. These techniques mimic processes in statistical mechanics and biology, respectively, and are the most popular meta-heuristics or general-purpose optimization strategies. A hybrid algorithm for circuit partitioning, which uses tabu search to improve the simulated annealing meta-heuristics, is also proposed and compared with pure tabu search and simulated annealing algorithms, and also with a genetic algorithm. The solutions obtained are compared and evaluated by including the hybrid partitioning algorithm in a parallel test generator which is used to determine the test patterns for the circuits of the frequently used ISCAS benchmark set.

Protocol Offload Evaluation Using Simics

This paper describes our work with Simics (Magnusson, 2002) in the evaluation of protocol offloading to keep low the communication overheads on the host CPU. Simics is a platform that can be used for a functional system simulation, including the application program, the operating system, the protocol stack and the device drivers. Nevertheless, network-oriented applications require a full-system simulation that includes not only the OS code, but also a model of the memory system and a detailed timing model of network DMA effects (Binkert, 2003). As Simics does not provide a detailed network I/O model, it could present some limitations that make it difficult an accurate network-oriented full-system simulation. Here we present the way we have overcome this problem

Swad: Web System for Education Support

This chapter presents a platform for supporting education tasks; we call it SWAD (in Spanish, it stands for Web-System for Education Support). This platform has been gradually developed during the last 7 years and is currently used at the University of Granada in more than 578 different subjects of different degrees. We describe here the various web services provided by the platform for students and educators, such as electronic index card, class photograph, document downloading, student self-assessment through multiple-choice exam, online checking of grades, internal web mail, discussion forums and electronic blackboard. The chapter also gives details about its implementation and provides evaluation statistics about its use and users’ opinions after testing the platform.

Parallel combinatorial optimization with evolutionary cooperation between processors

An evolutionary computation approach is used to learn online the rules that allow the processors in a parallel platform to cooperate by interchanging the local optima that they find while they concurrently explore different zones of the solution space. The cooperation of processors can greatly benefit the resolution of combinatorial optimization problems by decreasing their runtimes, by increasing the quality of the solutions obtained, or both. Moreover, as parallel computers are more and more accessible, the application of parallel processing to solve these problems becomes a practical and interesting alternative. As an example, a parallel optimization algorithm based on Boltzmann Machine has been used for a detailed description and evaluation of the proposed cooperation approach.

A New Offloaded/Onloaded Network Interface for High Performance Communication

The availability of multi-core processors and programmable NICs (Network Interface Cards), such as TOEs (TCP/IP Offloading Engines), provides new opportunities for designing efficient network interfaces to cope with the gap between the improvement rates of link bandwidths and microprocessor performance. This gap poses important challenges related with the high computational requirements associated to the traffic volumes and wider functionality that the network interface has to support. An opportunity to reach these goals comes from the exploitation of the parallelism in the communication path by distributing the protocol processing work across processors available in the computer, i.e. multi-core microprocessors and programmable NICs. Thus, alternatives such as offloading and onloading try to release host CPU cycles by this approach. Nevertheless, whereas onloading uses another general-purpose processor, either included in a multi-core microprocessor or in a symmetric multiprocessor (SMP), offloading takes advantage of processors in programmable network interface cards (NICs). Some experimental results demonstrate that the relative improvement on peak throughput offered by offloading and onloading depends on the rate of application workload to communication overhead, the message sizes, and on the characteristics of system architecture, more specifically the bandwidth of the buses and the way the NIC is connected to the system processor and memory. Thus, in this paper we propose a network interface that takes the advantages of both offloading and onloading approaches while avoids their respective drawbacks. The performance analyses done by using a full-system simulator, shows that, in the benchmarks and application used for the experiments, our hybrid interface improves the latency and bandwidth behavior of the onloading and offloading approaches.

Protocol offload analysis by simulation

In the last years, diverse network interface designs have been proposed to cope with the link bandwidth increase that is shifting the communication bottleneck towards the nodes in the network. The main point behind some of these network interfaces is to reach an efficient distribution of the communication overheads among the different processing units of the node, thus leaving more host CPU cycles for the applications and other operating systems tasks. Among these proposals, protocol offloading searches for an efficient use of the processing elements in the network interface card (NIC) to free the host CPU from network processing. The lack of both, conclusive experimental results about the possible benefits and a deep understanding of the behavior of these alternatives in their different parameter spaces, have caused some controversy about the usefulness of this technique. The contributions of this paper deal with the implementation and evaluation of offloading strategies and with the need of accurate tools for researching the computer system issues that, as networking, require the analysis of interactions among applications, operating system, and hardware. Thus, in this paper, a way to include timing models in a full-system simulator (Simics) to provide a suitable tool for network subsystem simulation is proposed. Moreover, we compare two kinds of simulators, a hardware description language level simulator and a full-system simulator (including our proposed timing models), in the analysis of protocol offloading at different levels. We also explain the results obtained from the perspective of the previously described LAWS model and propose some changes in this model to get a more accurate approach to the experimental results. From these results, it is possible to conclude that offloading allows a relevant throughput improvement in some circumstances that can be qualitatively predicted by the LAWS model.

Parameter Configurations for Hole Extraction in Cellular Neural Networks (CNN)

It is shown that the holes of the objects in an input image with a CT-CNN [1] or a DT-CNN [2] may be obtained in a single transient using just one linear parameter configuration. A set of local rules is given that describe how a CNN with a linear configuration may extract the hole of the objects of an input image in a single transient. The parameter configuration for DT-CNNs or for CT-CNNs is obtained as the solution of a single linear programming problem, including robustness as an objective. The tolerances to multiplicative and additive errors caused by circuit inaccuracies for the linear hole-extraction configurations proposed have been deduced. These tolerable errors have been corroborated by simulations. The tolerance to errors and the speed of the CT-CNN linear configuration proposed for hole extraction are compared with those of the CT-CNN nonlinear configuration found in the bibliography [3].