Antonio Gnudi

Analysis of Threshold Voltage Variability Due to Random Dopant Fluctuations in Junctionless FETs

An analytical formulation of the threshold voltage variance induced by random dopant fluctuations in junctionless transistors is derived for both cylindrical nanowire and planar double-gate structures under uniform channel and constant mobility approximation. Results from drift-diffusion-based numerical methods are in reasonable agreement also for large , including mobility variations, and for short gate lengths. The results clearly indicate that the threshold voltage fluctuations can become a concern with the reduction of the critical dimensions.

Physical Model of the Junctionless UTB SOI-FET

In this paper, we model the electrical properties of a junctionless (JL) ultrathin-body silicon-on-insulator field-effect transistor (SOI-FET), which has been proposed as a possible alternative to the junction-based SOI-FET. The model is based on improved depletion approximation, which provides a very accurate solution of Poissons equation and allows for the computation of the substrate, as well as the Si-body lower- and upper-surface potentials by an iterative procedure, which accounts for the back-oxide (BOX) charge and thickness and the potential drop within the substrate. The drain current is then computed versus gate, drain, and substrate voltages via integral expression and validated by comparison with technology computer-aided design simulation results. Analytical models of the field-effect-transistor threshold voltage and subthreshold slope are worked out against the substrate voltage, highlighting the effect of the substrate doping and BOX thickness on the aforementioned parameters. In essence, this work provides the physical background for better understanding of the JL SOI-FET and its assessment for logic applications.

Semianalytical Model of the Subthreshold Current in Short-Channel Junctionless Symmetric Double-Gate Field-Effect Transistors

A 2-D semianalytical solution for the electrostatic potential valid for junctionless symmetric double-gate field-effect transistors in subthreshold regime is proposed, which is based on the parabolic approximation for the potential and removes previous limitations. Based on such a solution, a semi-analytical expression for the current is derived. The potential and current models are validated through comparisons with TCAD simulations and are used to evaluate relevant short-channel effect parameters, such as threshold roll-off, drain-induced barrier lowering, and inverse subthreshold slope. The implications of different possible definitions of threshold voltage, either based on the potential in the channel or on a fixed current level, are discussed. Finally, a fully analytical simplification for the current is suggested, which can be used in compact models for circuit simulations.

TCAD Simulation of Hot-Carrier and Thermal Degradation in STI-LDMOS Transistors

Physically based models of hot-carrier stress and dielectric-field-enhanced thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated power devices over an extended range of stress biases and ambient temperatures. An analytical formulation of the distribution function accounting for the effects of the full band structure has been employed for hot-carrier modeling purposes. A quantitative understanding of the kinetics and local distribution of degradation is achieved, and the drift of the most relevant parameters is nicely predicted on an extended range of stress times and biases.

Graphene-Base Heterojunction Transistor: An Attractive Device for Terahertz Operation

For the first time, a simulation study is reported of a device formed by stacking an n+-Si layer (emitter), a monolayer graphene sheet (base), and a second n-Si layer (collector), operating as a graphene-base heterojunction transistor. The device differs from the recently proposed hot-electron graphene-base transistor (GBT), where graphene is sandwiched between the two dielectric layers, in the current flow being regulated mainly by thermionic emission over the potential-energy barrier, rather than by tunneling through the emitter-contact Schottky barrier. The simulations are based on a 1-D quantum transport model with the effective mass approximation and nonparabolic corrections. In addition to being much easier to fabricate compared with the GBT, the device is shown to be able to provide 104 ON/OFF current ratio, current densities well in excess of 0.1 A/μm2 and cutoff frequencies well above 1 THz, together with an intrinsic dc small-signal voltage gain larger than 10. Even though the simulation model is somewhat idealized, since ballistic transport is assumed and Si-graphene interfaces are ideal, our results show that this device is a serious competitor for high-frequency RF applications.

Drain-conductance optimization in nanowire TFETs

In this work we examine the problem of the nonlinear output characteristics of tunnel FETs, and the related small drain conductance at low drain voltage, which prevents rail-to-rail logic operation and severely degrades the device dynamic properties compared with standard CMOS FETs. The problem is investigated with the help of an analytical model which highlights the constraints of the device design by splitting the effects of the tunneling probability from the density of states in the source, channel and drain, and makes it possible to design a nanowire TFET by an appropriate selection of the material, nanowire size and degeneracy levels in the source and drain regions. So doing, we remove the above characteristics feature and recover a large drain conductance without degrading the subthreshold slope. The optimized device is numerically simulated using the k·p model, whose results are in fair agreement with the analytical one.

Graphene Base Transistors: A Simulation Study of DC and Small-Signal Operation

A simulation study aimed at investigating the main features in dc and small-signal operating conditions of the hot-electron graphene base transistor (GBT) for analog terahertz operation is presented. Intrinsic silicon is used as reference material. The numerical model is based on a self-consistent Schrödinger-Poisson solution, using a 1-D transport approximation and accounting for multiple-valley and nonparabolicity band effects. Some limitations in the extension of the saturation region and in the output conductance related to the finite quantum capacitance of graphene and to space charge effects are discussed. A small-signal model is developed that catches the essential physics behind the voltage gain and the cutoff frequency, which shows that the graphene quantum capacitance severely limits the former but not the latter. According to simulations carried out within the ballistic transport approximation, a 20-nm-long GBT can achieve at the same time a voltage gain larger than 10 and a cutoff frequency largely above 1 THz within a reasonably wide bias range.

Numerical investigation on the junctionless nanowire FET

In this work we investigate by numerical simulation the electrical properties of the junctionless nanowire field-effect transistor, which has recently been proposed as a possible alternative to the junction-based FET. The numerical model assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior by highlighting the features of the I-V and C-V characteristics, as well as the electrostatic potential and carrier concentration within the channel. Numerical results are compared with the experimental turn-on characteristics and are found to provide a generally-good agreement. Finally, we discuss the strengths and the limitations of this device as a possible candidate for future technology nodes.

TCAD predictions of linear and saturation HCS degradation in STI-based LDMOS transistors stressed in the impact-ionization regime

A new TCAD-based approach is used to investigate hot-carrier stress (HCS) effects, especially suited for power devices. Physically-based degradation models are used to determine the interface trap generation at different stress biases and ambient temperatures. Special attention has been given to the high current-voltage regimes, when significant self-heating effects and impact ionization play a relevant role. By monitoring the linear and saturation regimes of a rugged LDMOS at different stress biases and times, the spatial and energetic distribution of acceptor- and donor-type traps has been investigated for the first time confirming the experimental results.

Optimization and Analysis of the Dual n/p-LDMOS Device

A scalable Dual n/p-LDMOS device with interesting RSP versus VBD performance for voltage applications in the range of 20-120 V is identified through proper optimization. Three designs have been proposed, based on different process implementations. The physical behavior of the device is reviewed and analyzed. The current expansion induced by the bipolar conductance in the drift region at high gate and drain biases is fully explained. The thermal behavior in a worst case condition is investigated, and the reduction in performance in terms of current and safe-operating area are reported. The switching performance is addressed, showing very good transient times in any analyzed load condition.