Elena Gnani

Theory of the Junctionless Nanowire FET

In this paper, we model the electrical properties of the junctionless (JL) nanowire field-effect transistor (FET), which has been recently proposed as a possible alternative to the junction-based FET. The analytical model worked out here assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior. Most notably, it aims to clarify the motivation for its nearly ideal subthreshold slope and its excellent on-state current while being a depletion device with lower electron mobility due to impurity scattering. At the same time, the model clarifies a constraint binding the allowable value of the doping density per unit length and its impact on the overall device performance. The device variability and the parasitic source/drain resistances are identified as the most important limitations of the JL nanowire field-effect transistor.

Investigation of the Transport Properties of Silicon Nanowires Using Deterministic and Monte Carlo Approaches to the Solution of the Boltzmann Transport Equation

We investigate the transport properties of silicon- nanowire FETs by using two different approaches to the solution of the Boltzmann equation for the quasi-1-D electron gas, namely, the Monte Carlo method and a deterministic numerical solver. In both cases, we first solve the coupled Schrodinger-Poisson equations to extract the profiles of the 1-D subbands along the channel; next, the coupled multisubband Boltzmann equations are tackled with the two different procedures. A very good agreement is achieved between the two approaches to the transport problem in terms of mobility, drain-current, and internal physical quantities, such as carrier-distribution functions and average velocities. Some peculiar features of the low-field mobility as a function of the wire diameter and gate bias are discussed and justified based on the subband energy and wave-function behavior within the cylindrical geometry of the nanowire, as well as the heavy degeneracy of the electron gas at large gate biases.

Band-Structure Effects in Ultrascaled Silicon Nanowires

In this paper, we investigate band-structure effects on the transport properties of ultrascaled silicon nanowire FETs operating under quantum-ballistic conditions. More specifically, we expand the dispersion relationship epsiv(kappa) in a power series up to the third order in kappa2 and generate the corresponding higher order operator to be used within the single-electron Hamiltonian for the solution of the Schrodinger equation. We work out a hierarchy of nonparabolic models accounting for the following: 1) the shift of the subband edges and the change in the transport effective masses; 2) the higher order Hamiltonian operator; and 3) the splitting of the fourfold unprimed subbands in nanometer-size FETs. We then compute the device turn-on characteristics, the threshold shift versus diameter, and the subthreshold slope (SS) versus gate length. By compensating for the different threshold voltages, i.e., by reducing the turn- on characteristics to the same leakage current at zero gate bias, it turns out that the current discrepancies between the most general model and the bulk-parabolic model are contained within 20%. Finally, it turns out that the nonparabolic band structure gives an improved SS at the lowest gate lengths due to a reduced source-drain tunneling, reaching up to 30% enhancement.

Analysis of Threshold Voltage Variability Due to Random Dopant Fluctuations in Junctionless FETs

An analytical formulation of the threshold voltage variance induced by random dopant fluctuations in junctionless transistors is derived for both cylindrical nanowire and planar double-gate structures under uniform channel and constant mobility approximation. Results from drift-diffusion-based numerical methods are in reasonable agreement also for large , including mobility variations, and for short gate lengths. The results clearly indicate that the threshold voltage fluctuations can become a concern with the reduction of the critical dimensions.

Physical Model of the Junctionless UTB SOI-FET

In this paper, we model the electrical properties of a junctionless (JL) ultrathin-body silicon-on-insulator field-effect transistor (SOI-FET), which has been proposed as a possible alternative to the junction-based SOI-FET. The model is based on improved depletion approximation, which provides a very accurate solution of Poissons equation and allows for the computation of the substrate, as well as the Si-body lower- and upper-surface potentials by an iterative procedure, which accounts for the back-oxide (BOX) charge and thickness and the potential drop within the substrate. The drain current is then computed versus gate, drain, and substrate voltages via integral expression and validated by comparison with technology computer-aided design simulation results. Analytical models of the field-effect-transistor threshold voltage and subthreshold slope are worked out against the substrate voltage, highlighting the effect of the substrate doping and BOX thickness on the aforementioned parameters. In essence, this work provides the physical background for better understanding of the JL SOI-FET and its assessment for logic applications.

Semianalytical Model of the Subthreshold Current in Short-Channel Junctionless Symmetric Double-Gate Field-Effect Transistors

A 2-D semianalytical solution for the electrostatic potential valid for junctionless symmetric double-gate field-effect transistors in subthreshold regime is proposed, which is based on the parabolic approximation for the potential and removes previous limitations. Based on such a solution, a semi-analytical expression for the current is derived. The potential and current models are validated through comparisons with TCAD simulations and are used to evaluate relevant short-channel effect parameters, such as threshold roll-off, drain-induced barrier lowering, and inverse subthreshold slope. The implications of different possible definitions of threshold voltage, either based on the potential in the channel or on a fixed current level, are discussed. Finally, a fully analytical simplification for the current is suggested, which can be used in compact models for circuit simulations.

Low-Field Electron Mobility Model for Ultrathin-Body SOI and Double-Gate MOSFETs With Extremely Small Silicon Thicknesses

A number of experiments have recently appeared in the literature that extensively investigate the silicon-thickness dependence of the low-field carrier mobility in ultrathin-body silicon-on-insulator (SOI) MOSFETs. The aim of this paper is to develop a compact model, suited for implementation in device- simulation tools, which accurately predicts the low-field mobility in SOI single- and double-gate MOSFETs with Si thicknesses down to 2.48 nm. Such a model is still missing in the literature, despite its importance to predict the performance of present and future devices based on ultrathin silicon layers.

Design Considerations and Comparative Investigation of Ultra-Thin SOI, Double-Gate and Cylindrical Nanowire FETs

In this work we investigate the performance of fully-depleted silicon-on-insulator (SOI), double-gate (DG) and cylindrical nanowire (CNW) FETs, with the aim of establishing optimization procedures and appropriate scaling rules towards their extreme miniaturization limits. The simulation model fully accounts for quantum electrostatics; current transport is modeled by an improved quantum drift-diffusion approach supported by a new thickness-dependent mobility model which nicely fits the available measurements. The simple rule resulting from this investigation is that stringent short-channel effect constraints can be fulfilled at a constant oxide thickness of 2 nm, with Lg/t Si ap 5 for the SOI-FET, Lg/tSi ap 2 for the DG-FET, and Lg /tSi ap 1 for the CNW-FET

Quasi-Ballistic Transport in Nanowire Field-Effect Transistors

In this paper, we investigate quasi-ballistic transport in nanowire field-effect transistors (NW-FETs). In order to do so, we address the 1-D Boltzmann transport equation (BTE) and find its exact analytical solution for any potential profile with the constraint of dominant elastic scattering. A simulation code implementing a self-consistent Schrodinger-Poisson solver in the transverse direction and the present BTE solution in the longitudinal direction is worked out, providing the I-V characteristics of the NW-FET. Such characteristics are compared with those computed using a numerical BTE solver accounting for both inelastic and elastic collisions, and the two of them turn out to agree very nicely. From this comparison, it may be concluded that inelastic scattering plays a minor role for small-diameter FETs with device lengths in the decananometer range. Next, a methodology for the calculation of the transmission and backscattering coefficients is worked out for the first time starting from the scattering probabilities. The aforementioned coefficients turn out to be functions of the ratio between the carrier transit time and a suitably averaged momentum-relaxation time. Therefore, one of the main conclusions of this paper is that, so long as inelastic collisions are negligible, the so-called kT layer plays no role in 1-D quasi-ballistic carrier transport.

Optimization of n- and p-type TFETs Integrated on the Same

Design of a suitable technology platform is carried out in this paper for co-integration of simultaneously optimized n- and p-type tunnel field-effect transistors (TFETs). InAs/AlxGa1-xSb heterostructures are considered, and a 3-D full-quantum simulation approach is adopted to investigate the combined effect of Al mole fraction x and transverse quantization on band lineups at the heterojunction. Design optimization leads to a TFET pair with similar dimensions and feasible aspect ratios realized on the same InAs/Al0.05Ga0.95Sb platform. These devices exhibit average subthreshold slopes below 60 mV/dec and relatively high ON-currents of 270 (n-TFET) and 120 μA/μm (p-TFET) at a low-supply voltage VDD=0.4 V. Combined ON- and OFF-state performance of the proposed technology platform is expected to be compatible with low operating power applications, while potential candidates for low standby power scenarios are obtained by reducing TFET cross sections from 10 to 7 nm.