Antonio L. P. Rotondaro

Application of HfSiON as a gate dielectric material

Physical and electrical properties of HfSiON that make this material desirable as the gate dielectric in a standard metal–oxide–semiconductor flow are reported. Sputtering was used to deposit films with minimal low dielectric constant interface layers, equivalent oxide thicknesses below 13 A, and leakage current density at least two orders of magnitude lower than SiO2. The presence of nitrogen in the film enhances the thermal stability relative to HfSiO, and no crystallization was observed for anneals up to 1100 °C.

35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS

Results from the best reported PMOS transistor at a 37 nm gate length (Lg) built on a process with a recessed SiGe epitaxial layer are discussed. The process details include successful integration of SiGe at the drain extension (DE) location. A highly compressive SiGe layer, in close proximity to the channel, results in large hole mobility improvements. HRTEM based lattice parameter extractions confirm the compressive strain in the channel. In situ doped B in SiGe can be activated to a higher degree than implanted B in bulk Si resulting in further improvements from the lower DE resistance. Both changes combine to give an unprecedented 35% PMOS performance improvement. Process and device simulations that predict the observed parametric behavior quantitatively isolate the improvements to be /spl sim/ 28% from stress and 7% from DE resistance improvement.

Advanced CMOS transistors with a novel HfSiON gate dielectric

We report for the first time on short channel transistors fabricated using HfSiON, a new high-k gate dielectric material. HfSiON has superior electrical characteristics such as low leakage current relative to SiO/sub 2/, low interfacial trap density, electron and hole carrier mobilities /spl sim/80% of the universal curve at E/sub eff/>0.8 MV/cm and scalability to equivalent oxide thicknesses of less than 10 /spl Aring/. This material is also thermally stable up to 1100/spl deg/C in contact with poly Si, and exhibits boron blocking significantly better than SiO/sub 2/ and SiON. The results indicate that this material is a promising high-k gate dielectric with good transistor characteristics.

Composition control of Hf1−xSixO2 films deposited on Si by chemical-vapor deposition using amide precursors

Hafnium silicate (Hf1−xSixO2) films were deposited by metalorganic chemical-vapor deposition with composition x ranging from 0 to 1 using amide precursors in an organic solvent. The liquid precursors, tetrakis(diethylamido)hafnium, Hf[N(C2H5)2]4, and tetrakis(dimethylamido)silicon, Si[N(CH3)2]4, are compatible when mixed in solution, have high elemental purity, and exhibit a low halogen content. Thin oxide films were deposited with these precursors over a range of wafer temperatures from 400 to 600 °C with very low carbon and nitrogen incorporation. Control of the film composition is attained by changing the ratio of silicon concentration to hafnium concentration in the precursor solution for specific deposition conditions. Composition and growth rate are reported as a function of process condition. Interfacial layers of less than 10 A were observed by high-resolution transmission electron microscopy.

Characterization and comparison of the charge trapping in HfSiON and HfO/sub 2/ gate dielectrics

Charge trapping in HfSiON and HfO/sub 2/ gate dielectrics was studied using both DC and pulsed I/sub D/-V/sub G/ characterization techniques. The data shows a significant amount of hysteresis in HfO/sub 2/ but negligible instability in HfSiON. Constant voltage stress measurements of HfO/sub 2/ and HfSiON films show that the threshold voltage shift in HfO/sub 2/ films is as much as 10 times higher than that of HfSiON. Further, modeling of the time dependence of the threshold voltage shows that the trap capture cross section responsible for the instability of HfO/sub 2/ films is 10 times higher than the trap capture cross section of HfSiON. Our data indicate that amorphous HfSiON has better electrical stability than HfO/sub 2/.

Carrier mobility in MOSFETs fabricated with Hf-Si-O-N gate dielectric, polysilicon gate electrode, and self-aligned source and drain

A study of electron and hole mobilities for MOSFET devices fabricated with Hf-Si-O-N gate dielectric, polysilicon gate electrodes and self-aligned source and drain is presented. High effective electron and hole mobilities, 250 cm/sup 2//V/spl middot/s and 70 cm/sup 2//V/spl middot/s, respectively, were measured at high effective field (>0.5 MV/cm). The NMOSFETs have an equivalent oxide thickness (EOT) of 1.3 nm and the PMOSFETs have an EOT of 1.5 nm. The effect of interface engineering on the electron and hole mobilities is discussed.

Integrity of hafnium silicate/silicon dioxide ultrathin films on Si

Rapid thermal annealing at 1000 °C of (HfO2)1−x(SiO2)x pseudobinary alloy films deposited on Si were performed in N2 or O2 atmospheres. The effects on the atomic transport, structure, and composition were investigated using isotopic substitution of oxygen, high-resolution transmission electron microscopy, nuclear reaction analyses, narrow nuclear reaction resonance profiling, and grazing angle x-ray reflection.

Stability of zirconium silicate films on Si under vacuum and O2 annealing

The effect of postdeposition annealing in vacuum and in dry O2 on the atomic transport and chemical stability of chemical vapor deposited ZrSixOy films on Si is investigated. Rutherford backscattering spectrometry, narrow nuclear resonance profiling, and low energy ion scattering spectroscopy were used to obtain depth distributions of Si, O, and Zr in the films. The chemical environment of these elements in near-surface and near-interface regions was identified by angle-resolved x-ray photoelectron spectroscopy. It is shown that although the interface region is rather stable, the surface region presents an accumulation of Si after thermal annealing.

Evaluation of the positive biased temperature stress stability in HfSiON gate dielectrics

Electrical instability due to charge trapping in high-k materials is a primary concern for the usefulness of these films in future CMOS devices. This paper reports the effect of charge trapping on the threshold voltage and transistor drive current of devices made with HfSiON gate dielectric. Our results show that the physics of the charge trapping in HfSiON is unique and follows logarithmic dependence with time rather than usual exponential dependence. NMOS devices fabricated with HfSiON films show acceptable electrical stability for 10 years without substantial degradation of either the threshold voltage or the drive current.

Impact of interfacial layer on low-frequency noise of HfSiON dielectric MOSFETs

Low-frequency noise measurements and analysis were performed on n-channel MOSFETs with HfSiON as the gate-dielectric material. The role of SiON interfacial-layer thickness was investigated. It was observed that these fluctuations can be described by the unified flicker-noise model that attributes noise to correlated carrier-number/mobility fluctuations due to trapping states in the gate dielectric. The model was modified to include the effect of different gate stack layers on the observed noise. The carrier-number fluctuations were found to dominate over the correlated mobility fluctuations in the measured bias range and more so at the lower gate overdrives. The noise magnitude showed a decrease with increasing SiON interfacial-layer thickness. Furthermore, an inverse-proportionality relationship was revealed between the effective oxide trap density and SiON thickness.