Malcolm J. Bevan

Nitric oxide rapid thermal nitridation for Flash memory applications

Rapid thermal annealing in nitric oxide (RTNO) has long been used for the formation of ultrathin silicon oxynitride gate dielectrics. Nitric oxide (NO) furnace anneals are used in the formation of floating gate Flash memory transistor tunnel oxides. Nitrogen is thus, incorporated to improve the oxide reliability during program/erase cycling endurance and data retention. We present here a study of rapid thermal annealing and oxide growth in nitric oxide using Applied Materials single-wafer rapid thermal process (RTP) that enables the RTNO anneal to operate at higher temperatures compared to furnace, thereby allowing two times greater incorporation of nitrogen at the silicon/silicon dioxide interface. At 1200°C, a greater than 11% peak interface nitrogen concentration as measured by secondary ion mass spectroscopy (SIMS) in a 75 Angstrom SiON film is achieved. Reliability testing using a floating gate flash memory capacitor with minority carrier source (implants) test vehicle shows that this increase in the peak interface nitrogen results in an improvement in the tunnel oxides program/erase cycling endurance and data retention. For future memory devices, for example 3D memory devices, the use of direct RTNO oxide growth for dielectric formations is possible. In this case, higher temperatures allow the growth of thicker oxides in pure NO at 1200°C, with greater nitrogen incorporation.

Ultrathin SiO 2 interface layer growth

A variety of processes based on radical oxidation (N2O/H2) and spike RTO are investigated in this study to grow ultrathin SiO2 layers. Their process space is mapped out to cover regimes of interest for gate-last or gate-first integration of high k dielectrics with metal gates. Applieds Centura RTP chamber is found to be readily compatible with the requirements associated with 22/20nm CMOS technology.

The effect of interfacial oxide and high-κ thickness on NMOS V th shift from plasma-induced damage

Different thicknesses of interfacial oxide and high-κ were used to study the effects of plasma-induced damage (PID) in NMOS transistors. The thickness of high-κ HfO₂ was varied from 15Å to 25Å. The thickness of the interfacial layer (IL) with N₂O/H₂ was also varied from 5Å to 10Å. The threshold voltage (V_th) shift was observed to be greater in the thinner oxide using the same plasma condition. There was no significant effect with different IL thickness between 5Å and 10Å.

High-k Gate Stack: Improved Reliability through Process Clustering

Introduction High-k (HK) gate dielectric stack process integration is one of the most critical and challenging steps in the fabrication of CMOS since its adoption at the 45nm node [1]. A typical HK stack consists of the SiO2 interfacial layer (iL) followed by a nitrided and annealed HK dielectric. Both the nitridation and anneal results in an increased dielectric constant and improved HK and stability. It has been demonstrated in numerous papers that the quality of the HK bulk material and the interface with the iL plays a critical role in transistor’s reliability degradation. This degradation, generally due to electron trapping in the HK bulk and/or at the iL/HK interface, is quantified by Bias-Temperature Instability (BTI) which closely correlates to CV hysteresis [2]. Because of such reliability degradation concerns, clustering of the different HK stack process chambers in one single tool is critical in eliminating layer exposure to fab ambient that could result in HK bulk and interface quality degradation.