Antonio Rotondaro

The kink-related excess low-frequency noise in silicon-on-insulator MOST's

The phenomenology of the kink-related low-frequency (LF) noise overshoot in partially depleted (PD) silicon-on-insulator (SOI) MOS transistors is described in detail. The influence of various physical parameters is reported. Based on the observations, a comprehensive first-order theory for the feature is derived. The model is based on the charge fluctuations which are caused by deep-level assisted generation-recombination events in the depletion region of the transistor. It will be shown that the noise amplitude is proportional to the density of deep-level centers, while the peak position is a sensitive function of the saturation voltage. This follows from the postulated dependence of the capture time on the inverse substrate current. As will be shown, the standard expression for the multiplication current is in first order also valid for SOI MOSTs, both at room temperature and at 77 K. Simulations demonstrate that the proposed model correctly predicts the dependence of the noise overshoot on the measurement frequency, on the gate voltage, the temperature and on the device length. Finally, the spectroscopic potential of the feature will be outlined and possible ways to render the technique truly quantitative are pointed out. >

Impact of Fe and Cu contamination on the minority carrier lifetime of silicon substrates

The effects of trace amounts of Fe and Cu in p- and n-type silicon were investigated with microwave photoconductance decay and surface photovoltage. The wafers received controlled amounts of surface contamination of Fe and Cu that are relevant for ultralarge scale integrated technologies. The substrate doping type has a strong impact on the effect of the metallic impurities. Fe, as expected, strongly degrades the minority carrier li etime of p-type substrates. On the other hand, the impact of Fe on n-type silicon is at least one order of magnitude lower than on p-type. In contrast, Cu is highly detrimental to n-type material, but has no significant impact on the minority carrier properties of p-type silicon for the contamination levels studied.

H2O2 Decomposition and Its Impact on Silicon Surface Roughening and Gate Oxide Integrity.

In this study the impact of temperature and metal contamination on the stability of hydrogen peroxide in the two most common wet chemical cleaning mixtures for wafer process operations has been investigated. The stability of the caustic mixture ( NH4OH/H2O2/H2O) was found to be very sensitive to certain metallic contaminations in the sub-ppb range, while the stability of the acid mixture ( HCl/H2O2/H2O) is mainly influenced by non metallic, anionic components of the solution itself. We observed also a strong oscillating behaviour of the rate of the oxygen gas evolution caused by the decomposition of H2O2. Furthermore it was found, that the oxygen gas bubbles, formed by the decomposition of hydrogen peroxide cause a certain kind of micro-roughness on the silicon surface through a micro masking mechanism. In a series of experiments we could prove that this kind of surface roughness has a significant impact on the integrity of thin gate oxides.

Evidence of different conduction mechanisms in accumulation-mode p-channel SOI MOSFET's at room and liquid-helium temperatures

The threshold voltage for the three different conduction components of an accumulation-mode PMOS SOI were experimentally extracted at room and liquid-helium temperatures. A deep-depletion transient effect was observed to play an important role when one of the interfaces was in inversion, even at room temperature. An intuitive physical interpretation is given for the suppression of some current components at liquid-helium temperatures. In addition, a simple model for calculating the silicon-film thickness and the doping level is presented. >

Static and low-frequency noise characteristics of n+p junction diodes fabricated in different silicon substrates

This paper describes the impact of the starting Si material and thermal pretreatment on the static current-voltage characteristics of n+p junction diodes, using a combination of large-area, large-perimeter and gated diodes. In addition, the low-frequency noise spectrum in forward operation is studied for different p-type substrates. It is shown that in Czochralski-grown (Cz) wafers, the starting oxygen concentration plays a crucial role: highly precipitated high-oxygen diodes show a large bulk and perimeter leakage current and a high ideality factor m. Near ideal behaviour (m approximately=1) is found for epitaxial and floating-zone (FZ) grown substrates. The surface generation/recombination properties, however, are marginally affected by the interstitial oxygen content. Simultaneously, a clear impact of the substrate type on the low-frequency noise is observed, especially for high forward currents, whereby the lowest noise figures are obtained for epitaxial and FZ wafers. It is demonstrated that in Cz wafers both perimeter (surface) and bulk noise sources are active, explaining the higher noise level.

Recombination activity of iron‐related complexes in silicon studied by temperature dependent carrier lifetime measurements

Carrier recombination centers related with iron complexes in p‐type silicon are studied by microwave and light‐induced absorption techniques. Both thermal‐ and photoactivation are used to decompose iron–boron pairs and to study the impact on the recombination lifetime. Due to photodissociation of iron–boron pairs the lifetime increases for high level injection. Efficient recombination occurs via an acceptor level at Ec−0.29 eV as derived from the temperature dependence of carrier lifetime.

Simple method for the determination of the interface trap density at 77 K in fully depleted accumulation mode SOI MOSFETs

Abstract Siue5f8SiO 2 interface trap densities have a dominant impact on the electrical performance of MOS devices and are playing a crucial role in the understanding of the underlying device physics. For bulk MOSFETs a large variety of techniques are applicable to determine the interface trap density. Most of them remain valid for low temperature device operation. For SOI MOSFETs however, transient effects have to be taken into account. This paper discusses a new and simple technique, based on the threshold voltage shift as a function of the operating temperature, to determine the interface trap density in fully depleted accumulation mode SOI devices operating at cryogenic temperature. The validity of the technique will be demonstrated for 77 K device operation.

Transient effects in accumulation mode p-channel SOI MOSFET's operating at 77 K

This paper critically examines the conduction mechanisms in accumulation mode p-channel SOI MOSFETs operating at cryogenic temperatures. In particular, attention is given to the body current component, which in most cases is experimentally not observed at 77 K or 4.2 K. As will be demonstrated, both the body current and the back accumulation current show pronounced transient effects at low temperatures, which are related to the slow generation/recombination of minority carriers. This is caused by deep depletion from the front interface, which suppresses these current components. By the application of either a light pulse or a large drain voltage V/sub ds/ minority carriers are generated nearly instantaneously in the body region, rendering the body and the back accumulation components clearly visible. >

Outplating of metallic contaminants on silicon wafers from diluted acid solutions

The outplating behaviour of Fe and Cu was investigated for diluted solutions of HCl and HNO 3 . The deposition of the metallic contaminants was found to be strongly dependent on the type of surface that is exposed to the contaminated solution. Cu deposits heavily on bare silicon surfaces, whereas only low levels of Fe deposition are observed. On the other hand, on thermal oxide surfaces, the levels of deposited Fe are consistently higher than the Cu ones. The acid used appears to have no major impact on the deposition process. The pH of the solutions has a major effect on the Cu deposition and a minor effect on the Fe case.

A consistent experimental method for the extraction of the threshold voltage of SOI nMOSFETs from room down to cryogenic temperatures

Abstract A procedure for extracting the threshold voltage of SOI n MOSFETs is derived and experimentally validated for operation from room down to liquid helium temperature. This procedure provides a unique method for evaluating the threshold voltage of accumulation and enhancement mode SOI MOSFETs operating at low temperatures.