Antti Mäntyniemi

A CMOS time-to-digital converter with better than 10 ps single-shot precision

A high-precision CMOS time-to-digital converter IC has been designed. Time interval measurement is based on a counter and two-level interpolation realized with stabilized delay lines. Reference recycling in the delay line improves the integral nonlinearity of the interpolator and enables the use of a low frequency reference clock. Multi-level interpolation reduces the number of delay elements and registers and lowers the power consumption. The load capacitor scaled parallel structure in the delay line permits very high resolution. An INL look-up table reduces the effect of the remaining nonlinearity. The digitizer measures time intervals from 0 to 204 /spl mu/s with 8.1 ps rms single-shot precision. The resolution of 12.2 ps from a 5-MHz external reference clock is divided by means of only 20 delay elements.

A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method

This paper describes a time-to-digital converter (TDC) with ~1.2 ps resolution and ~327 mus dynamic range suitable for laser range-finding application for example. The resolution of ~1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method that resolves the time difference between two non-repetitive signals using binary search. The method utilizes a pair of digital-to-time converters (DTC), the propagation delay difference between which is implemented by digitally controlling the unit load capacitors of their delay cells, thus enabling sub-gate delay timing resolution. The rms single-shot precision, i.e., standard deviation sigma-value of the TDC is 3.2 ps, which is achieved by using an external integral nonlinearity look-up table (INL-LUT) for the interpolators. The power consumption is 33 mW at 100 MHz with a 3.3 V operating voltage. The prototypes were fabricated in a 0.35 mum CMOS process.

A CMOS time-to-digital converter based on a ring oscillator for a laser radar

An integrated ring oscillator based time-to-digital converter (TDC) for a pulsed time-of-flight laser rangefinder has been designed and tested. The time-to-digital conversion is based on counting the pulses of this eight-stage differential ring oscillator and additionally registering the state of its 16 phases at the arrival moment of the timing signals. The single-shot precision and the non-linearity of the TDC are better than 78.5ps and /spl plusmn/37ps, respectively and the current consumption of the time-to-digital converter was fabricated on the same chip with a receiver channel in a 0.35 /spl mu/m CMOS process.

An integrated 9-channel time digitizer with 30 ps resolution

An integrated 9-channel time digitizer with 30 ps RMS resolution, 496 /spl mu/s range, and 50 mW power consumption in 0.6 /spl mu/m CMOS uses a three-stage delay line interpolation and delay-generation principle that divides the 66 MHz clock period into 512 bins using only 45 delay elements.

A high resolution digital CMOS time-to-digital converter based on nested delay locked loops

This paper describes an integrated digital CMOS time-to-digital converter, TDC, with sub-gate-delay LSB width and 50 ps single shot resolution which equals 7 mm in time-of-flight laser range-finding measurement. The circuit was fabricated in an 0.8 /spl mu/m standard digital CMOS process. The measurement is based on a counter and a novel two step parallel interpolation that uses only 32 delay elements in two nested 16 element delay locked loops to provide 128 LSBs in the interpolator that resolves the timing within the reference clock cycle. The TDC has a fast conversion rate because of flash principle and requires no external calibration because the delay elements used for timing have been delay locked to the reference clock period. This TDC also has a very good temperature stability of 0.03 ps//spl deg/C and a low current consumption of <20 mA from a +5 V supply.

A Multichannel High-Precision CMOS Time-to-Digital Converter for Laser-Scanner-Based Perception Systems

A multichannel time-to-digital converter (TDC) implemented with 0.35-μm complementary metal-oxide-semiconductor technology that uses a low-frequency crystal as reference and measures the time intervals with counter and delay line interpolation techniques is described. The multichannel measurement architecture provides information on the time intervals between several timing signals. The circuit can be used for laser time-of-flight distance measurements, e.g., where it can determine time intervals between a transmitted laser pulse and several reflected pulses and also pulsewidths or rise times, to compensate for the timing walk error. This paper shows how several measurement channels can be integrated into one TDC without losing the measurement performance. The circuit offers a measurement precision that is better than 8 ps and a measurement range of up to 74 μs. In terms of laser distance measurement, its performance is equivalent to millimeter-level precision within an 11-km range.

Synchronization in a Multilevel CMOS Time-to-Digital Converter

Accurate time-to-digital conversion is typically based on determining the positions of the timing signals within the period of an accurate clock with digital delay-line interpolators. In order to save circuit area and to improve single-shot precision to the picosecond level, multilevel interpolators can be used. Timing signals are generally asynchronous with respect to the main clock, and thus, in order to obtain unambiguous and errorless results, careful attention should be given to the synchronization of the timing signals and various operating blocks and to the generation of the interpolation residue between the interpolators. This paper attempts to describe these problems in detail and suggests some solutions using a time-to-digital converter architecture based on two-level interpolation as a test vehicle, which demonstrates 6-ps rms single-shot precision in a measurement range of 1 ms.

A nonlinearity-corrected CMOS time digitizer IC with 20 ps single-shot precision

This paper describes the effect of the interpolator nonlinearity to the single-shot precision of a time digitizer and presents a method in which a look-up table (LUT) containing the measured integral nonlinearity (INL) of the interpolators is used as a correcting vector to improve the single-shot precision. The method was tested with a CMOS time digitizer IC with 496 /spl mu/s range, 29.59 ps LSB resolution and 28 ps RMS single-shot precision. The worst-case single-shot precision of 35 ps caused by the integral nonlinearity of the interpolators was reduced to /spl les/20 ps in the whole temperature range of -40/spl deg/C to +60/spl deg/C by using a single calibration LUT, which contains the measured INLs of the interpolators at room temperature.

A delay line based CMOS time digitizer IC with 13 ps single-shot precision

This paper introduces an integrated digital CMOS time-to-digital converter which measures time periods with picosecond-level resolution. The circuit was fabricated in a 0.35 /spl mu/m standard digital CMOS process. 13 ps rms single-shot precision was achieved by using a counter and a two-level nested DLL interpolation. Interpolators, which divide the cycle time of the 145 MHz reference clock to 512 pieces, provided 13.5 ps LSB width. The temperature drift was below 0.05 ps//spl deg/C. The power consumption with a 3.3 V operating voltage was 55 mW.

An Integrated Digital CMOS Time-to-Digital Converter with Sub-Gate-Delay Resolution

An integrated digital CMOS time-to-digital converter with sub-gate delay LSB width and 50 ps single-shot precision σ-value has been designed and implemented for a laser range-finding application. The measurement is based on a counter and a novel two-step parallel interpolation that uses only 32 delay elements to provide 128 LSBs in the interpolator within the reference clock cycle. The circuit was fabricated in the AMS 0.8 μm CMOS process and the current consumption of the circuit is <20 mA from a single +5 V supply.