Jussi-Pekka Jansson

A CMOS time-to-digital converter with better than 10 ps single-shot precision

A high-precision CMOS time-to-digital converter IC has been designed. Time interval measurement is based on a counter and two-level interpolation realized with stabilized delay lines. Reference recycling in the delay line improves the integral nonlinearity of the interpolator and enables the use of a low frequency reference clock. Multi-level interpolation reduces the number of delay elements and registers and lowers the power consumption. The load capacitor scaled parallel structure in the delay line permits very high resolution. An INL look-up table reduces the effect of the remaining nonlinearity. The digitizer measures time intervals from 0 to 204 /spl mu/s with 8.1 ps rms single-shot precision. The resolution of 12.2 ps from a 5-MHz external reference clock is divided by means of only 20 delay elements.

A Multichannel High-Precision CMOS Time-to-Digital Converter for Laser-Scanner-Based Perception Systems

A multichannel time-to-digital converter (TDC) implemented with 0.35-μm complementary metal-oxide-semiconductor technology that uses a low-frequency crystal as reference and measures the time intervals with counter and delay line interpolation techniques is described. The multichannel measurement architecture provides information on the time intervals between several timing signals. The circuit can be used for laser time-of-flight distance measurements, e.g., where it can determine time intervals between a transmitted laser pulse and several reflected pulses and also pulsewidths or rise times, to compensate for the timing walk error. This paper shows how several measurement channels can be integrated into one TDC without losing the measurement performance. The circuit offers a measurement precision that is better than 8 ps and a measurement range of up to 74 μs. In terms of laser distance measurement, its performance is equivalent to millimeter-level precision within an 11-km range.

Synchronization in a Multilevel CMOS Time-to-Digital Converter

Accurate time-to-digital conversion is typically based on determining the positions of the timing signals within the period of an accurate clock with digital delay-line interpolators. In order to save circuit area and to improve single-shot precision to the picosecond level, multilevel interpolators can be used. Timing signals are generally asynchronous with respect to the main clock, and thus, in order to obtain unambiguous and errorless results, careful attention should be given to the synchronization of the timing signals and various operating blocks and to the generation of the interpolation residue between the interpolators. This paper attempts to describe these problems in detail and suggests some solutions using a time-to-digital converter architecture based on two-level interpolation as a test vehicle, which demonstrates 6-ps rms single-shot precision in a measurement range of 1 ms.

A delay line based CMOS time digitizer IC with 13 ps single-shot precision

This paper introduces an integrated digital CMOS time-to-digital converter which measures time periods with picosecond-level resolution. The circuit was fabricated in a 0.35 /spl mu/m standard digital CMOS process. 13 ps rms single-shot precision was achieved by using a counter and a two-level nested DLL interpolation. Interpolators, which divide the cycle time of the 145 MHz reference clock to 512 pieces, provided 13.5 ps LSB width. The temperature drift was below 0.05 ps//spl deg/C. The power consumption with a 3.3 V operating voltage was 55 mW.

Solid-state 3D imaging using a 1nJ/100ps laser diode transmitter and a single photon receiver matrix.

A 3D imaging concept based on pulsed time-of-flight focal plane imaging is presented which can be tailored flexibly in terms of performance parameters such as range, image update rate, field-of-view, 2D resolution, depth accuracy, etc. according to the needs of different applications. The transmitter is based on a laser diode operating in enhanced gain-switching mode with a simple MOS/CMOS-switch current driver and capable of producing short (~100ps FWHM) high energy (up to nJ) pulses at a high pulsing rate. The receiver consists of 2D SPAD and TDC arrays placed on the same die, but in separate arrays. Paraxial optics can be used to illuminate the target field-of-view with the receiver placed at the focal plane of the receiver lens. To validate the concept, a prototype system is presented with a bulk laser diode/MOS driver operating at a wavelength of 870nm with a pulsing rate of 100kHz as the transmitter and a single-chip 9x9 SPAD array with 10-channel TDC as the receiver. The possibility of using this method as a solid-state solution to the task of 3D imaging is discussed in the light of the results derived from this prototype.

A single chip laser radar receiver with a 9×9 SPAD detector array and a 10-channel TDC

A single chip receiver for pulsed laser time-of-flight rangefinding applications has been realized in a standard 0.35um HV CMOS technology. It includes a 9×9 SPAD array and a 10-channel time-to-digital converter with 10ps single shot precision. Any of the 3×3 sub-arrays can be selected for simultaneous measurement. The selected SPAD array can be gated to be operative only within a selected time window in order to suppress dark and background light induced counts. Functional tests in a laser radar environment indicate full functionality over a range of nearly 80 metres.

Multiplying delay locked loop (MDLL) in time-to-digital conversion

This paper presents the use of a multiplying delay locked loop (MDLL) for delay line-based time interval measurement. The structure is introduced together with the theory behind the performance. Measurement results obtained with a MDLL-based time digitizer designed with 0.35 μm CMOS verify the operation and calculated performance of the device. This MDLL technique with modern CMOS technology makes longrange, high-resolution, linear time interval measurement possible with a small, simple one-level interpolation architecture.

CMOS technology scaling advantages in time domain signal processing

This paper compares two CMOS technologies, the robust 350nm version and its modern 28nm successor, in terms of time-domain signal processing parameters. The evaluated parameters; propagation delay, delay variation due to process and mismatch fluctuations, sensitivity to noise and area and power usage are crucial especially in measurement devices relying on precise timings, high precision time-to-digital converters, for example. Post-layout simulations show that the modern scaled technology offers superior speed, efficient area usage and low power consumption but suffers from considerable delay mismatch. Therefore applications relying on precise time domain signal processing do not always benefit from technology scaling.

A laser radar based on a “impulse-like” laser diode transmitter and a 2D SPAD/TDC receiver

A pulsed TOF laser radar has been implemented and its performance characterized. The transmitter applies a QW double-heterostructure laser diode producing 0.6 nJ/ 100 ps laser pulses at the central wavelength of ∼ 817 nm. The detector is a single-chip IC, manufactured in the standard 0.35 μm HV CMOS process, including a 9×9 SPAD array and a 10-channel TDC circuit. Both the SPAD array and the TDC circuit support a time gating feature allowing photon detection only to occur within a predefined time window. The SPAD array also supports the sub-array selection feature in order to respond to the laser spot wandering effect due to paraxial optics. A sub-array is a 3×3 SPAD array freely chosen within a 9×9 SPAD array. The characteristic measurement results demonstrate the measurement range of tens of meters with a linearity precision +/− 0.5 mm to the 11% target reflectivity and at pulsing frequency of 100 kHz. The distance dependent detection rate varies from 28% to 500%, thus providing a high measurement rate. The single-shot precision is ∼ 20 mm. The deteriorating impact of high-level background radiation conditions on the SNR has been demonstrated as well as a scheme to improve it by detector time gating.

Pulsed TOF laser rangefinding with a 2D SPAD-TDC receiver

A pulsed time-of-flight laser radar based on a high speed/energy optical transmitter and a SPAD-TDC receiver is presented. The transmitter employs a bulk double heterostructure laser diode operating in enhanced gain switching mode at a wavelength of ~870nm, giving ~1nJ/125ps optical pulses. The receiver is a single CMOS chip consisting of a 9×9 CMOS SPAD array and a 10-channel 10ps precision TDC. The 2D detector array releases the required precision and tolerances of the opto-mechanics of the radar. Any of the 3×3 sub-arrays within the 9×9 array can be selected for simultaneous measurement, and the selection can be altered flexibly during measurements, e.g. to follow movements of the target image at the detector surface. Adjustable-width time-gating windows of down to ~5ns can be used to suppress background hits. A single shot precision of ~170ps (FWHM) and a measurement range of tens of metres with non-cooperative targets have been achieved with an 18mm receiver aperture.