Antun Domic

Physical design and synthesis (panel): merge or die!

As IC fabrication capabilities extend down to sub-half-micron, the significance of interconnect delay and powerdissipation can no longer be ignored. Existing enhancements to synthesis and physical design tools (such as non-linear delay modeling, custom wire load models, back annotation of calculated delays, early oorplanning, post-layoutre-mapping and resizing) have not been able to solve theproblem. It thus remains that tradeoffs in logical and physical domains must be addressed in an integrated fashion.Huge business opportunities will be lost unless more revolutionary changes to design flow are made.This panel of experts will address the current split between logic synthesis and physical design and its effecton the design flow. It will then discuss possibilities formerging the two, or at least bringing them closer together.In particular, issues such as consistent wire load and timing models and algorithms which must be employed acrossthe design flow, EDA standards and common databasesto support the integration of layout and synthesis tools,evolving structured design styles that offer lower wiringoverhead, interconnect-driven logic synthesis, and timing-driven physical design will be discussed. Finally, the panelwill seek to highlight challenges and potential pitfalls that lie ahead.

Layout synthesis of MOS digital cells

Synthesis has been used to generate layouts for MOS circuits having a wide range of complexity, from a few to thousands of transistors. Until recently, automatic layout was confined to cell based approaches using a library of pre-laid out cells, such as standard cells or sea-of-gates primitives. The direct use of arbitrary cells, or the quick generation of new library items, is now receiving increased attention. This paper presents an overview of the main issues specific to the cell generation of MOS digital circuits.

Canonical computation without canonical representation

A representation of a Boolean function is canonical if, given a variable order, only one instance of the representation is possible for the function. A computation is canonical if the result depends only on the Boolean function and a variable order, and does not depend on how the function is represented and how the computation is implemented.In the context of Boolean satisfiability (SAT), canonicity of the computation implies that the result (a satisfying assignment for satisfiable instances and an abstraction of the unsat core for unsatisfiable instances) does not depend on the functional representation and the SAT solver used.This paper shows that SAT-based computations can be made canonical, even though the SAT solver is not using a canonical data structure. This brings advantages in EDA applications, such as irredundant sum of product (ISOP) computation, counter-example minimization, etc, where the uniqueness of solutions and/or improved quality of results justify a runtime overhead.

The Emergence of Design for Energy Efficiency: An EDA Perspective

As feature size is getting smaller, gate counts and clock speed are increasing, and so does power consumption. Designing for low power consuption has thus become mandatory for a large fraction of the ICs that will hit the market in the near future.

Design reuse (panel): fact or fiction

Design reuse is expected to be a key enabler for system designs in the 90s. Proponents claim that design reuse increases competitiveness through better quality, improved predictability and better productivity. On the other hand, skeptics say that design reuse is not realizable due to several barriers including rapid changes in technology, lack of standardized libraries and the presence of human, as opposed to technical barriers. Is design reuse a reality? How much is reused in practice? Where is it most applicable? Do concrete metrics exist for reusability? The panel will assess the track record of design reuse and discuss its status and future.

Panel: Looking backwards and forwards

Ten years ago, at 90 nanometers, EDA was challenged and deemed inadequate in dealing with increasing complexity, power consumption, and sub-wavelength lithography, thus harming the progress of mobile phones. Today, at 10 nanometers, integration capacity has increased by two orders of magnitude, power consumption has been successfully “tamed”, and 193 nanometer immersion lithography is still relied upon. Also thanks to EDA, tools, methodologies, and flows that were originally devised for design enablement for the emerging technology nodes, have been successfully redeployed at the established technology nodes, where they represent a critical design differentiation factor. However, the battleground is changing again: after the billions of phones, trillions of “things” lie ahead. Moving forward, emerging and established technology nodes, digital and analog, hardware and software will be equally critical. What is EDA doing and, more important, what should EDA do - and is not doing - in order for the next decade to be as great as the past one? This panel session, moderated by EPFL Professor Giovanni De Micheli, gathers academia, semiconductor, and EDA industry to discuss the challenges and requirements of the new era.

Panel: The future of electronics, semiconductors, and design in Europe

For more than a decade, Europe has been the wireless continent; today, wireless has almost completely shifted to the U.S. and Asia. This shift has had a profound impact on the electronic, semiconductor, and design ecosystem: long-time leaders have disappeared, or have abandoned the wireless business/market. Europe needs to re-invent itself once again. Is there a future for electronics, and IC design and manufacturing in Europe? If so, what are the applications, and the technologies that will bring Europe back to the top of the world leadership? This panel session, moderated by EPFL Professor Giovanni De Micheli, will gather executives from the semiconductor, IP, and R&D sectors to discuss the prospects of our industry in Europe.

Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads?

Crossroads have always been challenging: they require a decision; in Egyptian and Greek mythology they were often guarded by two sphinxes trying to cheat the traveler with their riddles. The two sphinxes, the knight and the knave, the lady and the tiger, are just few instances of difficult puzzles that have kept logicians and mathematicians busy for the last 5,000 years. Today, you are walking down Moores Law road when you come to a crossroads: one road brings you into the land of emerging technologies: 14, 10 and 7 nanometer, FDSOI, FinFET, 3D-IC,... beyond and below; the other road holds you into the land of established technologies: 28, 40, 65, and 90 nanometers, possibly even above, AM unlike the sphinxes, they will strive to provide you with honest advice about the “road conditions”, and you are allowed to ask multiple questions to them to figure out which road is the best for you.

Panel: what is EDA doing for trailing edge technologies?

Over the last decade, the semiconductor industry has advanced CMOS technology from 90 to 22/20 nanometers, and the EDA industry has developed a great deal of tools, methodologies, and flows to help “gigascale” design, implementation and verification, at these “leading edge” technology nodes. However, in 2010 approximately 75% of design starts used 130 nanometers or greater CMOS technologies [1], and 25% of wafers were fabricated using these “trailing edge” technologies [2]. There are possibly more designers working at 130 nanometers and above than at 90 nanometers and below, and there is certainly much more to electronics than just digital CMOS and microprocessors, and in order for the electronic industry to continue delivering on promises, “More than Moore” is needed, besides “More of Moore”. What is EDA doing - or what should EDA do - in order to help design implementation and verification at trailing edge technologies?

Panel and embedded tutorial — Logic synthesis and place and route: After 20 years of engagement, wedding in view?

The first half of the 80s marked a fundamental milestone in the history of design implementation: an amazing number of key research papers were published, in a relatively short period of time; suddenly, logic synthesis, placement, and routing algorithms reached a maturity level which enabled the birth of the first wave of modern EDA companies and design implementation tools: Silvar-Lisco, Cadence, Synopsys, Tangent…