Joseph Sawicki

DFM: where's the proof of value?

How can design teams employ new tools and develop response methodologies yet still stay within design budgets? How much effort does it require to be an early adopter and what kind of measurable results compensate for this effort? Panelists discuss how their design-for-manufacture (DFM) tools fit into a fixed design methodology, budget and timeline, and give examples of expected ROI (monetary, quality, reduced time-to-market, and comprehensive yield). The aim of this panel is to provide a serious comparison of related DFM technologies on the market and some idea of the cost and difficulty of integrating the tools into a fixed design budget and timeline. Specific results are cited, along with examples of expected ROI (monetary, quality, reduced time-to-market, and comprehensive yield enhancement). The audience should walk away with enough information to make an informed decision on which companies would make sense for their DFM challenges, to reach their own yield and throughput goals

DFM: magic bullet or marketing hype?

Over the past year interest in DFM has exploded in the semiconductor industry, and this despite the lack of a uniform working definition. The origin of this surge is shown to be related to three converging trends: increased design cost, shortened product lifetimes, and lower manufacturing yields for 130 nm technologies versus previous generations. A comparison to other industries reveals the distinct challenges attendant to semiconductor DFM and highlights the unique risks, which often necessitate non-intuitive solutions. Finally, the case is made to view DFM as a woven throughout the physical design flow, from cell design to mask data prep.

DFM: don't care or competitive weapon?

The external specifications of an IC (functions, clock rate, power consumption, etc.) determine the competitiveness of a product. To be successful and profitable in the IC business, designers need to “out-design” their competitors. Usually, Design-For-Manufacturing (DFM) is discussed as a yield improvement strategy, but what is the value of DFM from a competitive point of view? Can DFM gives designers a competitive lever by helping them decide how far to push a design without creating a manufacturing disaster? Can DFM be used to optimize designs rather than just identify hot spots?

Panel: Looking backwards and forwards

Ten years ago, at 90 nanometers, EDA was challenged and deemed inadequate in dealing with increasing complexity, power consumption, and sub-wavelength lithography, thus harming the progress of mobile phones. Today, at 10 nanometers, integration capacity has increased by two orders of magnitude, power consumption has been successfully “tamed”, and 193 nanometer immersion lithography is still relied upon. Also thanks to EDA, tools, methodologies, and flows that were originally devised for design enablement for the emerging technology nodes, have been successfully redeployed at the established technology nodes, where they represent a critical design differentiation factor. However, the battleground is changing again: after the billions of phones, trillions of “things” lie ahead. Moving forward, emerging and established technology nodes, digital and analog, hardware and software will be equally critical. What is EDA doing and, more important, what should EDA do - and is not doing - in order for the next decade to be as great as the past one? This panel session, moderated by EPFL Professor Giovanni De Micheli, gathers academia, semiconductor, and EDA industry to discuss the challenges and requirements of the new era.

Making the impossible: dealing with patterns throughout the design and manufacturing flow (Presentation Recording)

We have always described a semiconductor process node by aspects of pitch. Whether it is a minimum channel length, metal spacing, or as seems more common now, a number driven by the marketing department’s target message, everything came down to widths and spaces. Regardless as to how we got there, this matched well with both design and manufacturing views up though about 130nm. For designers, smaller transistors, and smaller interconnect pitches mapped to faster, smaller, and cheaper designs. For the fab, the widths and spaces mapped directly onto particle defect densities and defined their yield challenge. The world started to change somewhere in the 130nm to 90nm timeframe. Driven by the well-known difficulties involved in lithography and exacerbated by increased sensitivity in processes like CMP, design style-based or systematic defects became the major challenge to yieldramp, adding to the basic process ramp. Because of its involvement in the design, manufacturing, and test; EDA is in a unique position to contribute towards controlling, if not solving, the problem. We’ll look at: • Solutions in the DFT space that let us identify pattern failures hiding in yield loss • New methods in OPC that allow for process window expansion of problematic hot spots • Upcoming modeling technologies that target new pattern failure mechanisms in emerging nodes • New tools in the design spaces that can give designers visibility into the risks of production. The goal is a pattern aware EDA flow that minimizes risk, enhances manufacturing and quickly finds issues when they occur.

Panel: what is EDA doing for trailing edge technologies?

Over the last decade, the semiconductor industry has advanced CMOS technology from 90 to 22/20 nanometers, and the EDA industry has developed a great deal of tools, methodologies, and flows to help “gigascale” design, implementation and verification, at these “leading edge” technology nodes. However, in 2010 approximately 75% of design starts used 130 nanometers or greater CMOS technologies [1], and 25% of wafers were fabricated using these “trailing edge” technologies [2]. There are possibly more designers working at 130 nanometers and above than at 90 nanometers and below, and there is certainly much more to electronics than just digital CMOS and microprocessors, and in order for the electronic industry to continue delivering on promises, “More than Moore” is needed, besides “More of Moore”. What is EDA doing - or what should EDA do - in order to help design implementation and verification at trailing edge technologies?

DFM--EDA's Salvation or its Excuse for Being out of Touch with Engineering?

DFM/DFY has been recently touted as the high growth salvation of the EDA industry and it future direction. At present, DFM is heavily focused on the POST data creation correction of design data in a primitive level soft IP based SOC flow. The reality of the semiconductor community is they are shifting to a yield predictable, systems based hard megacell IP based SOC flow.

Forging Tighter Connections Between Design and Manufacturing in the Nanometer Age

As we dive deeper into nanometer technologies,we must rethink the waywe design.Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nanometer depths, making it more challenging than ever to achieve yield. In nanometer technology, DRC is not enough.