Anup Nayak

Programmable interconnect matrix architecture for complex programmable logic device

Architecture, circuitry and method for testing one or more integrated circuits and/or receiving test information therefrom

PLD configuration port architecture and logic

System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock

Configurable power controller

Architecture and logic to control a device without a JTAG port through a device with a JTAG port

Architecture for FPGAs

Circuit and method for dynamic in-rush current control in a power management circuit

Circuit for generating silicon ID for PLDS

PLD configuration architecture