Anup S. Mehta

A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors

In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme. Furthermore, the flip-flop family has the capability of easily incorporating logic functions with a small delay penalty. This feature greatly reduces the pipeline overhead, since each flip-flop can be viewed as a special logic gate that serves as a synchronization element as well.

Implementation of a 3rd-generation SPARC V9 64 b microprocessor

This 3rd-generation, superscalar processor, implementing the SPARC V9 64 b architecture, improves performance over previous processors by improvements in the on-chip memory system and circuit designs enhancing the speed of critical paths beyond the process entitlement. In the on-chip memory system, both bandwidth and latency are scaled. Keys to scaling memory latency are a sum-addressed memory data cache, which allows the average memory latency to scale by more than the clock ratio, and the use of a prefetch data cache. Memory bandwidth is improved by using wave-pipelined SRAM designs for on-chip caches and a write cache for store traffic. The chip operates at 800 MHz and dissipates <60 W from a 1.5 V supply. It contains 23 M transistors (12 M in RAM cells) on a 244mm/sup 2/ die. This paper contrasts this 7-metal-layer-aluminum, 0.15 /spl mu/m CMOS design with the previous generations designs. To deal with the growing microprocessor complexity, more aggressive circuit-techniques, interconnect delay optimization, crosstalk reduction, improved power and clock distribution schemes, and better thermal management are used.

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems

An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm2 die is implemented in a 65nm 8M process with low-power design techniques. Circuits to improve system performance under power constraints are discussed