Chaim Amir
Sun Microsystems
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Publication
Featured researches published by Chaim Amir.
IEEE Journal of Solid-state Circuits | 1999
Fabian Klass; Chaim Amir; Ashutosh Das; Kathirgamar Aingaran; Cindy Truong; Richard Wang; Anup S. Mehta; Ray Heald; Gin S. Yee
In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme. Furthermore, the flip-flop family has the capability of easily incorporating logic functions with a small delay penalty. This feature greatly reduces the pipeline overhead, since each flip-flop can be viewed as a special logic gate that serves as a synchronization element as well.
international solid-state circuits conference | 2000
Raymond A. Heald; Kathirgamar Aingaran; Chaim Amir; M. Ang; M. Boland; Ashutosh Das; P. Dixit; G. Gouldsberry; J. Hart; T. Horel; Wen-Jay Hsu; J. Kaku; Fabian Klass; Hang Kwan; Roger Lo; H. McIntyre; Anup S. Mehta; D. Murata; S. Nguyen; Yet-Ping Pai; S. Patel; K. Shin; Kenway Tam; S. Vishwanthaiah; J. Wu; Gin Yee; Hong You
This 3rd-generation, superscalar processor, implementing the SPARC V9 64 b architecture, improves performance over previous processors by improvements in the on-chip memory system and circuit designs enhancing the speed of critical paths beyond the process entitlement. In the on-chip memory system, both bandwidth and latency are scaled. Keys to scaling memory latency are a sum-addressed memory data cache, which allows the average memory latency to scale by more than the clock ratio, and the use of a prefetch data cache. Memory bandwidth is improved by using wave-pipelined SRAM designs for on-chip caches and a write cache for store traffic. The chip operates at 800 MHz and dissipates <60 W from a 1.5 V supply. It contains 23 M transistors (12 M in RAM cells) on a 244mm/sup 2/ die. This paper contrasts this 7-metal-layer-aluminum, 0.15 /spl mu/m CMOS design with the previous generations designs. To deal with the growing microprocessor complexity, more aggressive circuit-techniques, interconnect delay optimization, crosstalk reduction, improved power and clock distribution schemes, and better thermal management are used.
design automation conference | 1998
Julian Culetu; Chaim Amir; John MacDonald
In todays design of VLSI high speed circuits, frequency has a major impact on the number of repeaters that needs to be inserted. A microprocessor operating at less than 200 Mhz might require several hundred repeaters, while one operating at greater than 500 Mhz may require a number in the thousands. The following paper describes an efficient and simple way to automatically determine buffer placement based on maintaining equal transition time for all gate input signals across the net. A maximum allowable transition time is determined (limited by the frequency of the circuit), and correlated with the interconnect Elmore Delay. A Spice RC model having nodes with physical locations (X, Y coordinates) can be obtained by extraction tools providing standard parasitic format (SPF). This can then be used with the results of the algorithm for repeater placement to determine the exact physical location desired for each repeater.
Archive | 1999
Edgardo F. Klass; Chaim Amir
Archive | 1996
Edgardo F. Klass; David W. Poole; Chaim Amir; Raymond A. Heald
Archive | 2000
Kathirgamar Aingaran; Edgardo F. Klass; Chaim Amir; Chin-Man Kim
Archive | 1997
Edgardo F. Klass; Chaim Amir
Archive | 2000
Chaim Amir; Gin S. Yee
Archive | 1999
Julian Culetu; Chaim Amir
Archive | 1999
Anup S. Mehta; Chaim Amir; Edgardo F. Klass; Ashutosh Das