Anxiao Andrew Jiang

Joint rewriting and error correction in write-once memories

Both rewriting and error correction are important technologies for non-volatile memories, especially flash memories. However, coding schemes that combine them have been limited. This paper presents a new coding scheme that combines rewriting and error correction for the write-once memory model. Its construction is based on polar codes, and it supports any number of rewrites and corrects a substantial number of errors. The code is analyzed for the binary symmetric channel, and experimental results verify its performance. The results can be extended to multi-level cells and more general noise models.

Systematic Error-Correcting Codes for Rank Modulation

The rank-modulation scheme has been recently proposed for efficiently storing data in nonvolatile memories. In this paper, we explore [n, k, d] systematic error-correcting codes for rank modulation. Such codes have length n, k information symbols, and minimum distance d. Systematic codes have the benefits of enabling efficient information retrieval in conjunction with memory-scrubbing schemes. We study systematic codes for rank modulation under Kendalls T-metric as well as under the ℓ∞-metric. In Kendalls T-metric, we present [k + 2, k, 3] systematic codes for correcting a single error, which have optimal rates, unless systematic perfect codes exist. We also study the design of multierror-correcting codes, and provide a construction of [k + t + 1, k, 2t + 1] systematic codes, for large-enough k. We use nonconstructive arguments to show that for rank modulation, systematic codes achieve the same capacity as general error-correcting codes. Finally, in the ℓ∞-metric, we construct two [n, k, d] systematic multierror-correcting codes, the first for the case of d = 0(1) and the second for d = Θ(n). In the latter case, the codes have the same asymptotic rate as the best codes currently known in this metric.

Rank-modulation rewriting codes for flash memories

Current flash memory technology is focused on cost minimization of the stored capacity. However, the resulting approach supports a relatively small number of write-erase cycles. This technology is effective for consumer devices (smart-phones and cameras) where the number of write-erase cycles is small, however, it is not economical for enterprise storage systems that require a large number of lifetime writes. Our proposed approach for alleviating this problem consists of the efficient integration of two key ideas: (i) improving reliability and endurance by representing the information using relative values via the rank modulation scheme and (ii) increasing the overall (lifetime) capacity of the flash device via rewriting codes, namely, performing multiple writes per cell before erasure. We propose a new scheme that combines rank-modulation with rewriting. The key benefits of the new scheme include: (i) the ability to store close to 2 bits per cell on each write, and rewrite the memory close to q times, where q is the number of levels in each cell, and (ii) efficient encoding and decoding algorithms that use the recently proposed polar WOM codes.

A study of polar codes for MLC NAND flash memories

The increasing density of NAND flash memories makes data more prone to errors due to severe process variations and disturbance. The urgency to improve NAND flash reliability encourages searching for optimal channel coding methods. This paper reports our efforts towards a read channel for flash memories using polar coding. Our contributions include the solutions to several challenges raised when applying polar codes to NAND flash memories in practice. We propose efficient schemes for shortening both non-systematic and systematic polar codes, making polar codewords be easily adapted to flash page of any size. We demonstrate that the decoding performance of the shortened polar codes and LDPC codes are comparable using the data obtained by our NAND flash characterization platform. We show the feasibility of a practical adaptive decoding framework where it is not necessary to construct new polar codes for different channel parameters. Experimental results show that the decoding performance approaches the optimized performance where different codes are constructed for different channel conditions. To the best of our knowledge, this work is the first study of polar codes for error correction in flash memories.

Asymmetric Error Correction and Flash-Memory Rewriting Using Polar Codes

We propose efficient coding schemes for two communication settings: 1) asymmetric channels and 2) channels with an informed encoder. These settings are important in non-volatile memories, as well as optical and broadcast communication. The schemes are based on non-linear polar codes, and they build on and improve recent work on these settings. In asymmetric channels, we tackle the exponential storage requirement of previously known schemes that resulted from the use of large Boolean functions. We propose an improved scheme that achieves the capacity of asymmetric channels with polynomial computational complexity and storage requirement. The proposed non-linear scheme is then generalized to the setting of channel coding with an informed encoder using a multicoding technique. We consider specific instances of the scheme for flash memories that incorporate error-correction capabilities together with rewriting. Since the considered codes are non-linear, they eliminate the requirement of previously known schemes (called polar write-once-memory codes) for shared randomness between the encoder and the decoder. Finally, we mention that the multicoding scheme is also useful for broadcast communication in Martons region, improving upon previous schemes for this setting.

In-memory computing of Akers logic array

This work studies memories with the goal of exploring the concept of in-memory computing. Our point of departure is the 1972 classical study on logical arrays by Akers. We demonstrate a number of new ways for these arrays to simultaneously store information and perform logical operations. We first generalize these arrays to non-binary alphabets. We then show how a special structure of these arrays can both store values and output a sorted version of them. In addition we show how the array can tolerate or detect errors in the stored information.

Parallel programming of rank modulation

Rank modulation is a technique for representing stored information in an ordered set of flash memory cells by a permutation that reflects the ranking of their voltage levels. In this paper, we consider two figures of merit that can be used to compare parallel programming algorithms for rank modulation. These two criteria represent different tradeoffs between the programming speed and the lifetime of flash memory cells. In the first scenario, we want to find the minimum number of programming rounds required to increase a specified cell-level vector ℓ₀ to a cell-level vector corresponding to a target rank permutation τ, with no restriction on the maximum allowable cell level. We derive lower and upper bounds on this number, denoted by t₁*(τ, ℓ₀). In the second scenario, we seek an efficient programming strategy to achieve a cell-level vector ℓ(τ) consistent with the target permutation τ, such that the maximum cell level after programming is minimized. Equivalently, this strategy maximizes the number of information update cycles supported by the device before requiring a block erasure. We derive upper bounds on the minimum number of programming rounds required to achieve cell-level vector ℓ(τ), denoted by t₁(τ, ℓ₀), and propose a programming algorithm for which the resultant number of programming rounds is close to t₂*(τ, ℓ₀).

Error Correction and Partial Information Rewriting for Flash Memories

This paper considers the partial information rewriting problem for flash memories. In this problem, the state of information can only be updated to a limited number of new states, and errors may occur in memory cells between two adjacent updates. We propose two coding schemes based on the models of trajectory codes. The bounds on achievable code rates are shown using polar WOM coding. Our schemes generalize the existing rewriting codes in multiple ways, and can be applied to various practical scenarios such as file editing, log-based file systems and file synchronization systems.

Rank-Modulation Rewrite Coding for Flash Memories

The current flash memory technology focuses on the cost minimization of its static storage capacity. However, the resulting approach supports a relatively small number of program-erase cycles. This technology is effective for consumer devices (e.g., smartphones and cameras) where the number of program-erase cycles is small. However, it is not economical for enterprise storage systems that require a large number of lifetime writes. The proposed approach in this paper for alleviating this problem consists of the efficient integration of two key ideas: 1) improving reliability and endurance by representing the information using relative values via the rank modulation scheme and 2) increasing the overall (lifetime) capacity of the flash device via rewriting codes, namely, performing multiple writes per cell before erasure. This paper presents a new coding scheme that combines rank-modulation with rewriting. The key benefits of the new scheme include: 1) the ability to store close to 2 bit per cell on each write with minimal impact on the lifetime of the memory and 2) efficient encoding and decoding algorithms that make use of capacity-achieving write-once-memory codes that were proposed recently.

Data archiving in 1x-nm NAND flash memories: Enabling long-term storage using rank modulation and scrubbing

The challenge of using inexpensive and high-density NAND flash for archival storage was posed recently for reducing data center costs. However, such flash memory is becoming more susceptible to noise, and its reliability issues has become the major concern for its adoption by long-term storage systems. This paper studies the system-level reliability of archival storage that uses 1x-nm NAND flash memory. We analyze retention error behavior, and show that 1x-nm MLC and TLC flash do not immediately qualify for long-term storage. We then implement the rank modulation (RM) scheme and memory scrubbing (MS) for retention period (RP) enhancement. The RM scheme provides a new data representation using the relative order of cell voltages, which provides higher reliability against uniform asymmetric threshold voltage shift due to charge leakage. Results show that the new representation reduces raw bit error rate (RBER) by 45% on average, and using RM and MS together provides up to 196, 171, 146 and 121 years of RPs for blocks with 0, 25, 50 and 75 program/erase cycles, respectively.