Ara Bicakci

A CMOS line driver for ADSL central office applications

An ADSL central office (CO) line driver utilizing a single 6-V supply is described. The line driver output produces a 20-V/sub ppd/ signal to deliver a 40-V/sub ppd/ swing to a 100-/spl Omega/ line. The adoption of an active termination, a dynamic supply control circuit technique, and deep n-well devices at the output stage of the line driver is key in achieving such a large voltage swing in a 0.25-/spl mu/m CMOS process. In order to ensure reliability of the output devices, the dynamic supply control algorithm is designed to activate only one lift amplifier at each signal path of the differential line driver at any given time. A transformer turns ratio of 1:2.4 ensures both reliability and optimal power dissipation in the presence of system losses. The total power dissipation of the line driver is 700 mW when discrete multitone signals with a crest factor of 15 dB were used to deliver 20.4 dBm to a 100-/spl Omega/ line.

A 700 mW CMOS line driver for ADSL central office applications

A dual-channel analog front-end for ANSI/ETSI standards compliant VDSL in 0.25/0.5/spl mu/m 1P 5M CMOS is presented. The chip includes a non-linearity cancelling multi-path line driver achieving -76dBc 3rd harmonic distortion at 12MHz, a 75mW continuous-time multi-bit 3rd-order self-calibrating /spl Sigma//spl Delta/ ADC, a 14b current-steering DAC with PSD mask post filter, a 0-35dB variable-gain amplifier with adjustable hybrid, and a 12ps jitter LC PLL.

A /spl Delta//spl Sigma/ DAC with reduced activity data weighted averaging and anti-jitter digital filter

A CMOS DAC with a 4th order digital DeltaSigma modulator achieves more than 94dB SFDR and 84dB SNDR for a conversion bandwidth of 2.2MHz and an over-sampling ratio of eight. A post modulator digital FIR filter increases jitter immunity and a reduced activity data-weighted-averaging (RADWA) scheme improves SFDR without any noticeable degradation in the SNDR. The prototype chip that contains the RA-DWA circuitry, the core analog DAC, and the clock generation circuitry is built in 0.13 mum standard digital CMOS process. The analog and digital power consumptions are 70mW and 2mW respectively. The DAC area is 1times1.2 mm2