Cormac S. Conroy
Qualcomm
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Featured researches published by Cormac S. Conroy.
international solid-state circuits conference | 2005
Ozan E. Erdogan; R. Gupta; Dennis G. Yee; Jacques C. Rudell; Jin-Su Ko; Roger Brockenbrough; Emilia Lei; Joo Leong Tham; Hongbing Wu; Cormac S. Conroy; Beomsup Kim
A 0.18 /spl mu/m CMOS single-chip fully integrated quad-band GSM/GPRS transceiver is presented. The low-IF receive section achieves -110dBm sensitivity at the antenna and -15dBm IIP3. The offset-frequency PLL transmitter achieves 1.2/spl deg/ rms phase noise, -65dBc modulation mask at 400kHz, and -165dBc/Hz noise at 20MHz. The chip occupies 17mm/sup 2/ and dissipates 95mA/112mA in receive/transmit mode.
IEEE Journal of Solid-state Circuits | 2005
Jinwook Kim; Jeongsik Yang; Sangjin Byun; Hyunduk Jun; Jeongkyu Park; Cormac S. Conroy; Beomsup Kim
This work presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5Gb/s for a single 10-Gbit eXtended Attachment Unit Interface (XAUI) in a standard 0.18-/spl mu/m CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than <4.5/spl times/10/sup -15/ while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.
international solid-state circuits conference | 2009
Aristotele Hadjichristos; Marco Cassia; Hong Sun Kim; C. H. Park; Kevin Hsi-Huai Wang; W. Zhuo; Bahman Ahrari; Roger Brockenbrough; JG(陈金根) Chen; Conor Donovan; R. Jonnalagedda; Jong-Uk Kim; Jin-Su Ko; Hee Choul Lee; Sang Oh Lee; Emilia Lei; Thinh Cat Nguyen; Tzu-Wang Pan; S. Sridhara; Wenjun Su; Hongyan Yan; Jian Yang; Cormac S. Conroy; Charles J. Persico; Kamal Sahota; Beomsup Kim
The large commercial success of multiband multimode 3rd-generation cellular products has driven single-chip integration, SAW-filter reduction and low power consumption. State-of-the-art solutions require quad-band EGSM combined with multiband WCDMA/HSPA receiver diversity and integrated GPS. Compact form factors make single-chip SAW-less solutions highly desirable. A Quad-Band GSM/EDGE-only transceiver was published in [1], and Triple-Band WCDMA-only transceiver solutions were published in [2–4]. This work describes the first multiband WCDMA/HSPA/EGPRS single-chip transceiver with GPS and receiver diversity. This device supports UMTS Bands 1,2,3,4,5,6,8,9,10 and GSM/EDGE 800, 900, 1800, 1900MHz Bands. It is implemented in cost-effective 0.18µm RF CMOS technology and uses a reduced number of TX and RX SAW filters.
international solid-state circuits conference | 2005
Jacques C. Rudell; Ozan E. Erdogan; Dennis G. Yee; Roger Brockenbrough; Cormac S. Conroy; Beomsup Kim
A 0.18 /spl mu/m CMOS fifth-order harmonic-rejection G/sub m/C filter is presented for use in offset PLL transmitter applications. Using an in-situ calibration scheme with a tuning accuracy of 2% and a maximum calibration time of 90 /spl mu/s, this filter tunes from 52 to 151MHz and draws 7mA from a 1.8V supply while achieving an IIP3 of 7dBV with an output noise floor of 9.3 /spl mu/V in a 30kHz BW.
international solid-state circuits conference | 2004
Jeongsik Yang; Jinwook Kim; Sangjin Byun; Cormac S. Conroy; Beomsup Kim
This paper presents a quad-channel serial-link transceiver which provides 12.5 Gb/s full duplex raw data rate for a single 10 Gb XAUI interface. A mixed-mode LMS adaptive equalizer is adopted, which achieves 3 dB SNR improvement over pre-emphasis techniques. A delay-immune CDR circuit recovers the receive clock with 64 ps-pp jitter. The IC consumes 718 mW at 3.125 Gb/s/ch with full duplex data rate.
european solid-state circuits conference | 2008
Kenneth Charles Barnett; Harish S. Muthali; Susanta Sengupta; Yunfei Feng; Bo Yang; Zhije Xiong; Tae Wook Kim; James Jaffee; Cormac S. Conroy
A multi standard direct conversion receiver for digital video broadcast application is presented. This receiver supports MediaFLOtrade, DVB-H and ISDB-T standards. Broadband multi-standard operation is achieved with a reconfigurable LNA, broadband mixer, programmable bandwidth baseband filter, wide tuning range LC VCO with a fully integrated fractional-N synthesizer. A high linearity signal path enables concurrent operation with GSM transmitter. Out of band transmitter (TX) blockers (DCS/IMT, Bluetooth) are attenuated by a novel integrated elliptic low pass filter. The receiver is implemented in 0.18 mum CMOS process. In MediaFLOtrade mode this design achieves a cascaded noise figure (NF) of 2.7 dB and IIP3 of -8.2 dBm in the highest gain mode. In DVB-H mode this design achieves a cascaded noise figure of 2.5 dB and IIP3 of -3.3 dBm in the highest gain mode. The peak power dissipation is 162 mW and 190 mW (@2.1 V) in MediaFLOtrade and DVB-H mode respectively.
Archive | 2002
Beomsup Kim; Cormac S. Conroy
Archive | 2008
Michael Kohlmann; Tae Hea Nahm; Beomsup Kim; Cormac S. Conroy
Archive | 2013
George Joseph; Peter S. Marx; Eric P. Bilange; Leyla S. Celebi; Gaurav Lamba; Cormac S. Conroy; Praveen Dua; Jayal Madhukumar Mehta
Archive | 2009
Liang Zhao; Roger Brockenbrough; Michael Kohlmann; Cormac S. Conroy; Anup Savla