Arash Farhadi Beldachi

Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling

This paper investigates the energy reductions possible in commercially available FPGAs configured to support voltage, frequency and logic scalability combined with power gating. Voltage and frequency scaling is based on in-situ detectors that allow the device to detect valid working voltage and frequency pairs at run-time while logic scalability is achieved with partial dynamic reconfiguration. The considered devices are FPGA-processor hybrids with independent power domains fabricated in 28 nm process nodes. The test case is based on a number of operational scenarios in which the FPGA side is loaded with a motion estimation core that can be configured with a variable number of execution units. The results demonstrate that voltage scalability reduces power by up to 60 percent compared with nominal voltage operation at the same frequency. The energy analysis show that the most energy efficiency core configuration depends on the performance requirements. A low performance scenario shows that serial computation is more energy efficient than the parallel configuration while the opposite is true when the performance requirements increase. An algorithm is proposed to combine effectively adaptive voltage/logic scaling and power gating in the proposed system and application.

Run-time power and performance scaling with CPU-FPGA hybrids

This paper investigates how a wide dynamic range of performance and power levels can be obtained in commercially available state-of-the-art hybrid FPGAs that include ARM embedded processors and independent power domains. Adaptive voltage and frequency scaling obtained with embedded in-situ detectors in a closed loop configuration is employed to scale performance and power in the FPGA fabric under processor control. The initial results are based on a high-performance motion estimation processor mapped to the FPGA fabric and show that it is possible to obtain energy savings higher than 60% or alternatively double performance at nominal energy. The available voltage and frequency margins in the device create a large number of performance and energy states with scaling possible at run-time with low overheads.

Accurate power control and monitoring in ZYNQ boards

ZYNQ devices combine a dual-core ARM Cortex A9 processor and a FPGA fabric in the same die and in different power domains. In this paper we investigate the run-time power scaling capabilities of these devices using of-the-shelf boards and proposed accurate and fine-grained power control and monitoring techniques. The experimental results show that both software and hardware methods are possible and the right selection can yield different results in terms of control and monitoring speeds, accuracy of measurement, power consumption, and area overhead. The results also demonstrate that significant power margins are available in the FPGA device with different voltage configurations possible. This can be used to complement traditional voltage scaling techniques applied to the processor domain to obtain hybrid energy proportional computing platforms.

Run-time power and performance scaling in 28 nm FPGAs

The ability of scaling power and performance at run-time enables the creation of computing systems in which energy is consumed in proportion of the work to be done and the time available to do it. These systems favour active energy-efficient states in which useful computation is performed at low energy instead of using inactive energy savings modes that incur large latency and energy penalties to enter and exit modes in which the system is halted. This is particular useful in servers that spend most of their time at around 30% utilisation and are rarely fully idle or at maximum utilisation. A feature of an energy proportional computing system is that it must exhibit a wide dynamic range with multiple levels of energy and performance available. In this context, this study investigates how these levels can be obtained in commercially available state-of-the-art 28 nm field-programmable gate arrays (FPGAs) and characterises its benefits. Adaptive voltage and frequency scaling is employed to deliver proportional performance and power in these FPGA devices. The results reveal that the available voltage and frequency margins create a large number of performance and energy states with scaling possible at run-time with low overheads. Power savings of up to 64.98% are possible maintaining the original performance at a lower voltage.

Fully SDN-enabled all-optical architecture for data center virtualization with time and space multiplexing

Virtual data center (VDC) solutions provide an environment that is able to quickly scale up, and where virtual machines and network resources can be quickly added on-demand through self-service procedures. VDC providers must support multiple simultaneous tenants with isolated networks on the same physical substrate. The provider must make efficient use of its available physical resources while providing high-bandwidth and low-latency connections to tenants with a variety of VDC configurations. This paper utilizes state-of-the-art optical network elements to provide high-bandwidth optical interconnections and develop a VDC architecture to slice the network and the compute resources dynamically, to efficiently divide the physical network between tenants. We present a data center virtualization architecture with a softwaredefined networking controlled all-optical data plane combining optical circuit switching and a time-shared optical network. Developed network orchestration dynamically translates and provisions VDCs requests onto the optical physical layer. The experimental results show the provisioned bandwidth can be varied by adjusting the number of time slots allocated in the time-division multiplexing (TDM) network. These results lead to recommendations for provisioning TDM connections with different performance characteristics. Moreover, application-level optical switch reconfiguration time is also evaluated to fully understand the impact on application performance in VDC provision. The experimental demonstration confirmed that the developed VDC approach introduces negligible delay and complexity on the network side.

eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip

This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The sub-networks can generate non-regular global topologies which are also supported by the XTRANC algorithm. XTRANC is especially suitable for dynamically reconfigurable networks mapped to commercial FPGAs in which additional links are added to the mesh topology at run-time to reduce congestion depending on application behaviour and resource availability. XTRANC allows the insertion of links as requested by different parts of the application without centralized control and this research shows that despite this dynamic behaviour the routing algorithm remains deadlock free.

Exploring dynamically reconfigurable multicore designs with NoRC designer

This paper presents a toolset named NoRC (Network on a Reconfigurable Chip) designer and IP infrastructure designed to investigate the effects of partial dynamic reconfiguration in multicore designs mapped to commercial FPGAs. Dynamic reconfiguration means in this context that tiles and communication routers can be modified at run-time adapting to changes in application requirements, operating conditions and/or process variations. The NoRC system is oriented at avoiding any centralized control with functions mapped to tiles at runtime depending on processing capabilities and location. The dynamic nature of the platform means that following a request for an application from an external host any idle tile can be configured as a master able to make additional requests to nearby tiles or as a slave able to service the requests. NoRC designer is used in this paper to investigate possible task mapping strategies suitable for this type of adaptive platform and also the power and partial reconfiguration overheads of commercial FPGAs.

Reconfigure router design and evaluation for the FPGA-friendly SoCWire network-on-chip

This paper extends the System-on-Chip Wire (SoCWire) Network-On-Chip (NoC) with a reconfigurable router suitable for building FPGA-based NoC. Different configurations of the SoCWireRouter with a varying number of local and multi-dimensional ports have been used to create a number of equivalent networks. The system is prototyped in a FPGA-based PCIexpress board with the NoC connected to a softcore processor that acts as system master and monitor. The evaluation of equivalent networks for a fixed number of computing nodes under a synthetic and realistic traffic loads indicates the ideal SoCWireRouter topology depends on the design objectives and expected traffic pattern.