Jose Luis Nunez-Yanez

Adaptive stochastic routing in fault-tolerant on-chip networks

Due to shrinking transistor geometries, on-chip circuits are becoming vulnerable to errors, but at the same time on-chip networks are required to provide reliable services over unreliable physical interconnects. A connection oriented stochastic routing (COSR) algorithm has been used on one NoC platform that provides excellent fault-tolerance and dynamic reconfiguration capability. A probability model has been built to analyze the COSR algorithm. According to the model, the performance may be improved by implementing a self learning mechanism in each router. Thus a new adaptive stochastic routing (ASR) algorithm is proposed whereby each router learns the network status from acknowledgement flits and stores the outcomes in a routing table. Simulation of both algorithms reveals that the ASR algorithm shows a higher path reservation success rate and a larger maximal accepted traffic than the COSR algorithm. The simulations also show that the learning procedures are accurate and that both algorithms are fault-tolerant to intermittent/permanent errors.

Differential patterning of neuronal, glial and neural progenitor cells on phosphorus-doped and UV irradiated diamond-like carbon

Diamond-like carbon (DLC) is an attractive biomaterial for coating human implantable devices. Our particular research interest is in developing DLC as a coating material for implants and electrical devices for the nervous system. We previously reported that DLC is not toxic to N2a neuroblastoma cells or primary cortical neurons and showed that phosphorus-doped DLC (P:DLC) could be used to produce patterned neuron networks. In the present study we complement and extend these findings by exploring patterning of dorsal root ganglion (DRG) explants, human neural progenitor cells (hNPC) and U-87 astroglioma cells on P:DLC. Further P:DLC data is provided to highlight that P:DLC can be used as an effective coating material for in vitro multi-electrode arrays (MEAs) with potential for patterning groups of neurons on selected electrodes. We also introduce ultraviolet (UV) irradiation as a simple treatment to render DLC neurocompatible. We show that UV:DLC can be used to support patterned and unpatterned cortical neuron growth. These findings strongly support the use of DLC as tailorable and tuneable substrate to study neural cell biology in vitro and in vivo. We conclude that DLC is a well-suited candidate material for coating implantable devices in the human nervous system.

Video Super-Resolution Using Generalized Gaussian Markov Random Fields

In this letter, we present the first application of the Generalized Gaussian Markov Random Field (GGMRF) to the problem of video super-resolution. The GGMRF prior is employed to perform a maximum a posteriori (MAP) estimation of the desired high-resolution image. Compared with traditional prior models, the GGMRF can describe the distribution of the high-resolution image much better and can also preserve better the discontinuities (edges) of the original image. Previous work that used GGMRF for image restoration in which the temporal dependencies among video frames has not considered. Since the corresponding energy function is convex, gradient descent optimization techniques are used to solve the MAP estimation. Results show the super-resolved images using the GGMRF prior not only offers a good enhancement of visual quality, but also contain a significantly smaller amount of noise.

Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems

An investigation into an effective and low-complexity adaptive routing strategy based on stochastic principles for an asynchronous network-on-chip platform that includes dynamically reconfigurable computing nodes is presented. The approach is compared with classic deterministic routing and it is shown to have good properties in terms of throughput and excellent fault-tolerance capabilities. The challenge of how to deliver reliability is one of the problems that multiprocessor system architects and manufactures will face as feature sizes and voltage supplies shrink and deep-submicron effects reduce the ability to carry out deterministic computing. It is likely that a new type of deep-submicron complex multicore systems will emerge which will be required to deliver high performance within strict energy and area budgets and operate over unreliable silicon. Within this context, the paper studies an on-chip communication infrastructure suitable for these systems.

A configurable and programmable motion estimation processor for the H.264 video codec

This work presents a programmable, configurable motion estimation processor for the H.264 video coding standard, capable of handling the processing requirements of high definition (HD) video and suitable for FPGA implementation. The programmable aspect of the processor follows the ASIP (application specific instruction set processor) approach with a instruction set targeted to accelerating block matching motion estimation algorithms. Configurability relates to the ability to optimize the microarchitecture for the selected algorithm and performance requirements through varying the number and type of execution units at compile time.

Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding

This paper presents a flexible and scalable motion estimation processor capable of supporting the processing requirements for high-definition (HD) video using the H.264 Advanced Video Codec, which is suited for FPGA implementation. Unlike most previous work, our core is optimized to execute all existing fast block matching algorithms, which we show to match or exceed the inter-frame prediction performance of traditional full-search approaches at the HD resolutions commonly in use today. Using our development tools, such algorithms can be described using a C-style syntax which is compiled into our custom instruction set. We show that different HD sequences exhibit different characteristics which necessitate a flexible and configurable solution when targeting embedded applications. This is supported in our core and toolset by allowing designers to modify the number of functional units to be instantiated. All processor instances remain binary compatible so recompilation of the motion estimation algorithm is not required. Due to this optimization process, it is possible to match the processing requirements of the selected motion estimation algorithm to the hardware microarchitecture leading to a very efficient implementation.

Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs

This paper investigates the limits of adaptive voltage scaling (AVS) applied to commercial FPGAs which do not specifically support voltage adaptation. An adaptive power architecture based on a modified design flow is created with in-situ detectors and dynamic reconfiguration of clock management resources. AVS is a power-saving technique that enables a device to regulate its own voltage and frequency based on workload, process and operating conditions in a closed-loop configuration. It results in significant improved energy profiles compared with dynamic voltage frequency scaling (DVFS) in which the device uses a number of pre-calculated valid working points. The results of deploying AVS in FPGAs with in-situ detectors shows power and energy savings exceeding 85 percent compared with nominal voltage operation at the same frequency. The in-situ detector approach compares favorably with critical path replication based on delay lines since it avoids the need of cumbersome and error-prone delay line calibration.

Dynamic Reconfiguration Optimisation with Streaming Data Decompression

This paper presents a high performance reconfiguration controller enhanced with the use of streaming lossless decompression in its data path. Two reconfiguration controllers are designed, the first is a generic controller that utilises standard concepts such as Direct Memory Access, burst mode transfer of data and interrupts to maximise throughput. This controller is then improved by the inclusion of a streaming decompression engine optimised for the Internal Configuration Access Port (ICAP) interface. This new controller significantly improves the reconfiguration speed of the system and throughputs of up to 385 Mbytes/sec are recorded. As power and energy become very important constraints in the system design, an investigation of the overheads associated with the use of the reconfiguration controller are experimentally quantified and presented.

Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture

This paper presents a novel dynamically reconfigurable hardware architecture for lossless compression and its optimization for space imagery. The proposed system makes use of reconfiguration to support optimal modeling strategies adaptively for data with different dimensions. The advantage of the proposed system is the efficient combination of different compression functions. For image data, we propose a new multi-mode image model which can detect the local features of the image and use different modes to encode regions with different features. Experimental results show that our system improves compression ratios of space image while maintaining low complexity and high throughput.

Enabling accurate modeling of power and energy consumption in an ARM-based System-on-Chip

Abstract Motivated by the importance of energy consumption in mobile electronics this work describes a methodology developed at ARM for power modeling and energy estimation in complex System-on-Chips (SoCs). The approach is based on developing statistical power models for the system components using regression analysis and extends previous work that has mainly focused on microprocessor cores. The power models are derived from post-layout power-estimation data, after exploring the high-level activity space of each component. The models are then used to conduct an energy analysis based on realistic use cases including web browser benchmarks and multimedia algorithms running on a dual-core processor under Linux. The obtained results show the effects of different hardware configurations on power and energy for a given application and that system level energy consumption analysis can help the design team to make informed architectural trade-offs during the design process.