Archana Chidanandan

Area-Efficient NEDA Architecture for The 1-D DCT/IDCT

A new distributed arithmetic has been applied to the 1-D DCT to produce a low power, high throughput architecture. In this paper, we apply NEDA to the even-odd decomposition matrices of the 8times8 forward and inverse DCT. We show that, with the proposed approach, the number of adders required for the adder array for the forward DCT and the inverse DCT is fewer than required if NEDA is applied directly to the 8times8 DCT and IDCT matrices. This reduction results in power savings, without decreasing the throughput. Also, for the inverse DCT, the number of adder stages is reduced, resulting in faster decoding

In their words: student feedback on an international project collaboration

In this paper, we describe a collaborative course experience between students from universities in the USA and Turkey. Student teams worked together on a software engineering project for a non-profit organization based in Turkey. The students learned valuable skills in team-work, collaboration-facilitating software tools and working with peers from a different culture and a different time-zone. At the end of the course, in a focus group, students were asked for feedback regarding the course and its outcomes. In this paper, we describe the course from the student perspective. From this, and the instructors experiences we provide a list of guidelines.

Implementation of NEDA-based DCT architecture using even-odd decomposition of the 8 × 8 DCT matrix

New Distributed Arithmetic has been been applied to the 1-D DCT to produce a low power, high throughput architecture. In previous work, we applied NEDA to the even-odd decomposition matrices of the 8 × 8 forward and inverse DCT. With the proposed approach, the number of adders required for the adder array for the forward DCT and the inverse DCT is fewer than required if NEDA is applied directly to the 8 × 8 DCT and IDCT matrices. This reduction results in few adders needed, without decreasing the throughput. Also, for the inverse DCT, the number of adder stages is reduced, resulting in faster decoding. In this paper, we present the results of the implementation for the forward DCT using 4:2 compressor trees where needed to decrease the delay and show the results obtained from synthesizing the design in 0.18¿ technology using Cadence BuildGates.

Adopting pen-based technology to facilitate active learning in the classroom: is it right for you?

In this work, we identify factors that should be examined when considering the adoption of collaboration-facilitating software and hardware and also determine what needs to be done to facilitate the use of this technology in the classroom.

Panel session - pen-based computing in the engineering and science classroom: Implementation scenarios from three institutions

As digital ink technology continues to make an impact on the technical classroom, faculty members are exploring the different strategies for using this technology to improve student learning. The purpose of this panel is to demonstrate how faculty members are implementing this technology in engineering and science classrooms at three different institutions: Rose-Hulman Institute of Technology, University of Texas at Austin, and University of Vermont. The panel is designed to show both experienced pen computing users and those who are new to the field the different ways this versatile technology may be employed. In addition to the demonstrations, the presenters will discuss the pedagogical implications that result from the implementations. Faculty who are interested in both the pedagogy and assessment of pen-based computing in the classroom should find the session informative and useful.

Enhanced Parallel Interference Cancellation using Decorrelator for the base-station receiver

Multi-user detection is a paradigm that is used to enhance the performance of the receivers in cellular networks in terms of Bit Error Rate (BER), capacity and near-far effect. Parallel Interference Cancellation is the choice for most current multi-user detection receivers because of its simplicity in implementation and good qualitative parameters. Decorrelator-based Parallel Interference Cancellation (PIC) has been proposed to improve the performance of the PIC receiver. In this paper, we make an important observation about the determination of the Decorrelator that makes it feasible for it to be used in conjunction with PIC in the base-station receiver.

Work in progress - an online support system for women in Computer Science

In this work, we propose the creation of an online social network with the following objectives: (a) provide a platform for our female students to interact with our alumnae, (b) provide a platform for high school students in the Indiana neighborhood to interact with our female students and alumnae. This social network will facilitate a support system for our current students, our alumnae, and young women who are interested in pursuing careers in computer science. In the long term, we anticipate that the interactions made possible by the social network will be extended to encompass other educational institutions.

Novel systolic array architecture for the decorrelator using conjugate gradient for least squares algorithm

The decorrelator is a linear transform that can be used in multi-user detection receivers in cellular networks to increase the capacity of the base-station receiver. It has been shown that the decorrelation operation can be performed using iterative methods that do not require computation-intensive inverse matrix computation. We propose a high throughput systolic array architecture for the decorrelator receiver, which meets the throughput demands of 3G mobile communications systems.