Aric Shorey

Development of substrates for through glass vias (TGV) for 3DS-IC integration

Through-substrate vias (TSV) are critical for Three-Dimensional Stacked Integrated Circuits (3DS-IC) integration. While silicon traditionally has been used in this application, glass has properties that make it a very intriguing material for through substrate via applications. We note that the term glass describes a broad material set, with a wide range of properties driven by composition. For example, compositional changes allow tailoring of mechanical and thermal properties. Furthermore, novel forming processes available today enable reduction or elimination of time consuming and costly thinning or polishing processes, as well as opportunities to more easily scale the footprint of the substrate. Significant progress has been made to develop techniques to provide suitable through holes for vias in different glass compositions, which leverages the versatility of glass to create a substrate for TSV.

Advancements in fabrication of glass interposers

There is growing interest in applying glass as an interposer substrate for 2.5D/3D as well as component substrates for radio frequency (RF) applications. The list of important advantages provided by glass in these applications include material properties (e.g. electrical performance, ability to adjust coefficient of thermal expansion (CTE) to improve reliability) as well as the significant opportunities for cost advantages that glass based solutions provide over other approaches. The feasibility of fabricating high quality holes in glass substrates has been demonstrated. While work in hole fabrication continues, additional efforts to demonstrate and mature downstream processing of glass substrates has accelerated. These include hole metallization and redistribution layers (RDL) in both wafer and panel formats, as well as initial characterization and demonstration of reliability. Significant progress in these areas is reported here.

Fabrication of 3D-IC interposers

Over the past several years, the semiconductor industry has seen some tremendous developments in using glass as an interposer substrate. Glass has many properties that make it an ideal substrate for interposer substrates such as: ultra-high resistivity, low dielectric constant, ultra-low electrical loss and adjustable coefficient of thermal expansion (CTE) that allows management of 3D-IC stacks. Regardless of technical performance, any glass based solution must also provide significant cost advantages in substrate material, via formation, and subsequent processing. Cost-Effective Solutions In this paper, we will cover how fusion formed glass provides cost-effective solutions for the manufacturing of interposer materials for as-formed 100 μm precision substrate with a pristine surface, without the need for polishing, thus eliminating the manufacturing steps for polishing and thinning. Design Considerations For effective implementation of glass substrates, processing costs for through-glass-vias (TGV) on ultra-thin glass is also a challenge. This paper will reference data from several different designs to demonstrate the impact of design on Cornings TGV process cost relative to silicon solutions. It will also highlight processing lessons learned in fabricating TGV interposers from bare glass into complete packaged test vehicles and their impact on cost. Via Capabilities Furthermore, glasses via formation capabilities have dramatically improved over the past several months. Fully populated wafers with >100,000 through and blind holes (25 μm diameter) are fabricated today with 20μm diameters. We report on the significant enhancements demonstrated on important quality parameters. We will also report on strength parameters measured on TGV wafers and positive implications with respect to product reliability.

Metrology for characterization of wafer thickness uniformity during 3DS-IC processing

There is a constant desire to increase substrate size in order to improve cost effectiveness of semiconductor processes. As the wafer diameter has increased from 2” to 12”, the thickness has remained largely the same, resulting in a wafer form factor with inherently low stiffness. Gravity induced deformation becomes important when using traditional metrology tools and mounting strategies to characterize a wafer with such low stiffness. While there are strategies used to try to reduce the effects of deformation, gravitational sag provides a large source of error in measurements. Furthermore, glass is becoming an important material for substrates in semiconductor applications and metrology tools developed for use for characterizing silicon are inherently less suitable for glass. Using a novel mounting strategy and a measurement technique based on optical interference provides an opportunity to improve on the methodologies utilized to characterize wafer flatness (warp, bow) and total thickness variation (TTV). Not only can the accuracy of the measurement be improved, using an interference based technique allows for full wafer characterization with spatial resolution better than 1 mm, providing substantially more complete wafer characterization.

Through glass vias (TGV) and aspects of reliability

Glass as a substrate for electronics packaging has many potential benefits, including the ability to tailor the thermomechanical and electrical properties of the glass to meet the demands of a given application. Because this process may entail modifications to the chemical composition of the glass, the impact of the composition changes to the long term reliability of the electronic package should be carefully considered. Here, two different compositions of glass are examined with regards to their use as a glass interposer, and specific aspects of their reliability are tested. A glass interposer design was fabricated on glass substrates of two different coefficients of thermal expansion (CTEs), 3 and 8 ppm/°C. This design has 35 × 120 μm through glass vias (TGVs) and front and backside Cu routing metal. The routing metal and TGVs form electrically testable daisy chains. Samples of these glass interposers were subjected to 1000 thermal cycles from - 40 °C to 125 °C to compare the two different glass compositions with regard to their long term reliability. Electrical testing on daisy-chained arrays of 400 TGVs each before and after thermal cycling showed no failures of the structures. In a separate test, Cu interdigitated test structures with 10 μm lines/space were fabricated on glass substrates of the same two types, on silicon with a thermal oxide layer, and also on fused silica. The leakage current between isolated structures was tested before and after 96 hrs of biased highly accelerated stress testing (HAST). The results indicate that for the glass substrate with a CTE of 8 ppm/°C, a barrier layer is necessary between the substrate and Cu metallization to prevent Cu migration.

Glass interposer substrates: Fabrication, characterization and modeling

There is growing interest in applying glass as a substrate for 2.5D/3D applications. Glass has many material properties that make it well suited for interposer substrates. Glass based solutions provide significant opportunities for cost benefits by leveraging economies of scale as well as forming substrates at design thickness. A lot of work is being done to validate the value of glass as an interposer substrate. One important area is the electrical performance of glass relative to silicon. Because glass is an insulator, it is expected to have better electrical performance than silicon. Electrical characterization and electrical models demonstrate the advantages of the insulating properties of glass, and its positive impact on functional performance. Further advantages are anticipated in reliability performance, because of the ability to adjust thermal properties such as coefficient of thermal expansion (CTE) of glass. Modeling results demonstrating these improvements will be presented. Additionally, significant progress has been made in the demonstration of glass interposer fabrication. Fully patterned wafers and panels with through holes and blind holes are being fabricated today. Leveraging existing downstream processes for metallization on these substrates is also important for cost effectiveness and ease of transition into production. Progress on demonstrating the ability to leverage existing downstream processes to make functional glass interposers using both through and blind via technology will be presented.

Glass wafer mechanical properties: A comparison to silicon

The billion dollar silicon industry is built on the extreme uniformity, chemical, and mechanical strength of perfect crystals of silicon configured in the shape of a wafer for standard integrated circuit processing. Silicon is an ideal substrate for creating transistors. Thinning the silicon integrated circuit (IC) substrate has now become a common process approach to maintain the trend established by Moores law and to meet the packaging form factor required by consumer applications. The thinned silicon wafer can be used in a stand alone thin form factor package, or combined with other thinned silicon device wafers to create a three dimensional stack IC structure (3D-IC). A thinned silicon IC wafer is very difficult to handle. Therefore it generally requires the use of a carrier substrate attached with a temporary bonding method as an aid to handling

Substrate-integrated waveguides in glass interposers with through-package-vias

This paper presents, for the first time, substrate-integrated waveguides (SIWs) in ultra-thin glass with through-package-vias (TPVs). An SIW operating at 20 GHz was designed in bare glass substrates to support the dominant TE10 mode and to avoid exciting TE20 mode. The simulated propagation constant confirmed the proper design for one-mode excitation, while the distributions of electromagnetic fields and surface current were examined and they exhibited similar patterns to those in dielectric-filled rectangular waveguides. Furthermore, the simulated S-parameter shows that the insertion loss at 20 GHz is 0.67 dB/cm, and 100% relative bandwidth was achieved. Finally, the impacts of TPV taper and the variability of the glass thickness and TPV pitch on the electrical performance of the SIW in glass interposers with TPVs were studied and presented.

Through-glass interposer integrated high quality RF components

High quality and compact RF devices, using the half mode substrate integrated waveguide (HMSIW) architecture loaded with a complementary split ring resonator (CSRR), are implemented on a glass interposer layer, which therefore serves as an interconnection layer and as a host medium for integrated passive RF components. Compared with the silicon interposer approach, which suffers from large electrical conductivity and therefore substrate loss, the glass interposer has advantages of low substrate loss, allowing high quality interconnection and passive circuits, and low material and manufacturing costs. Corning fusion glass is selected as the substrate to realize the compact CSRR-loaded HMSIW resonators and bandpass filters (BPFs) working under the principle of evanescent wave amplification. Two and three pole bandpass filters are designed for broadband operation at 5.8 GHz. Thru glass vias (TGVs) are used to define the side-wall of the substrate integrated waveguiding structure. Surface micromachining techniques are used to fabricate the proposed devices. The variations of the external quality factor (Qe) of the resonator and the internal coupling coefficient (M) of the coupled resonators are studied for filter design. Operation of the filters at 5.8 GHz with a fractional bandwidth (FBW) of more than 10% for an in-band return loss of better than 20 dB and an low insertion loss of less than 1.35 dB has been obtained, which is not feasible with a usual Si interposer approach. Measurement results are presented from 2 to 10 GHz and show good agreement with simulated ones.

Glass carrier wafers for the silicon thinning process for stack IC applications

The performance of the temporary bond and debond process for wafer thinning is critical for 3D system integration. In the thinning process, the silicon wafer will be bonded face down to a carrier and then ground down to the desired thickness. After this process step, device wafer and carrier wafer will be separated again for additional downstream processing, such as separation and assembly. The work presented here will highlight the importance of high precision carriers and metrology techniques used to characterize and qualify these materials and, most importantly, the impact these have on the TTV of a bonded stack. The ability to leverage all of these tools to provide bonded stacks with extremely low TTV and impact on Si wafers after thinning operations will be demonstrated.