Scott Pollard

Development of substrates for through glass vias (TGV) for 3DS-IC integration

Through-substrate vias (TSV) are critical for Three-Dimensional Stacked Integrated Circuits (3DS-IC) integration. While silicon traditionally has been used in this application, glass has properties that make it a very intriguing material for through substrate via applications. We note that the term glass describes a broad material set, with a wide range of properties driven by composition. For example, compositional changes allow tailoring of mechanical and thermal properties. Furthermore, novel forming processes available today enable reduction or elimination of time consuming and costly thinning or polishing processes, as well as opportunities to more easily scale the footprint of the substrate. Significant progress has been made to develop techniques to provide suitable through holes for vias in different glass compositions, which leverages the versatility of glass to create a substrate for TSV.

Advancements in fabrication of glass interposers

There is growing interest in applying glass as an interposer substrate for 2.5D/3D as well as component substrates for radio frequency (RF) applications. The list of important advantages provided by glass in these applications include material properties (e.g. electrical performance, ability to adjust coefficient of thermal expansion (CTE) to improve reliability) as well as the significant opportunities for cost advantages that glass based solutions provide over other approaches. The feasibility of fabricating high quality holes in glass substrates has been demonstrated. While work in hole fabrication continues, additional efforts to demonstrate and mature downstream processing of glass substrates has accelerated. These include hole metallization and redistribution layers (RDL) in both wafer and panel formats, as well as initial characterization and demonstration of reliability. Significant progress in these areas is reported here.

Fabrication of 3D-IC interposers

Over the past several years, the semiconductor industry has seen some tremendous developments in using glass as an interposer substrate. Glass has many properties that make it an ideal substrate for interposer substrates such as: ultra-high resistivity, low dielectric constant, ultra-low electrical loss and adjustable coefficient of thermal expansion (CTE) that allows management of 3D-IC stacks. Regardless of technical performance, any glass based solution must also provide significant cost advantages in substrate material, via formation, and subsequent processing. Cost-Effective Solutions In this paper, we will cover how fusion formed glass provides cost-effective solutions for the manufacturing of interposer materials for as-formed 100 μm precision substrate with a pristine surface, without the need for polishing, thus eliminating the manufacturing steps for polishing and thinning. Design Considerations For effective implementation of glass substrates, processing costs for through-glass-vias (TGV) on ultra-thin glass is also a challenge. This paper will reference data from several different designs to demonstrate the impact of design on Cornings TGV process cost relative to silicon solutions. It will also highlight processing lessons learned in fabricating TGV interposers from bare glass into complete packaged test vehicles and their impact on cost. Via Capabilities Furthermore, glasses via formation capabilities have dramatically improved over the past several months. Fully populated wafers with >100,000 through and blind holes (25 μm diameter) are fabricated today with 20μm diameters. We report on the significant enhancements demonstrated on important quality parameters. We will also report on strength parameters measured on TGV wafers and positive implications with respect to product reliability.

Glass interposer substrates: Fabrication, characterization and modeling

There is growing interest in applying glass as a substrate for 2.5D/3D applications. Glass has many material properties that make it well suited for interposer substrates. Glass based solutions provide significant opportunities for cost benefits by leveraging economies of scale as well as forming substrates at design thickness. A lot of work is being done to validate the value of glass as an interposer substrate. One important area is the electrical performance of glass relative to silicon. Because glass is an insulator, it is expected to have better electrical performance than silicon. Electrical characterization and electrical models demonstrate the advantages of the insulating properties of glass, and its positive impact on functional performance. Further advantages are anticipated in reliability performance, because of the ability to adjust thermal properties such as coefficient of thermal expansion (CTE) of glass. Modeling results demonstrating these improvements will be presented. Additionally, significant progress has been made in the demonstration of glass interposer fabrication. Fully patterned wafers and panels with through holes and blind holes are being fabricated today. Leveraging existing downstream processes for metallization on these substrates is also important for cost effectiveness and ease of transition into production. Progress on demonstrating the ability to leverage existing downstream processes to make functional glass interposers using both through and blind via technology will be presented.

RFID tag readability for tracking fiber optic connections in Data Centers

Data Centers have a very large number of optical fiber cables and connections, and there is a need to track the connectivity of these to assure proper network interconnection among the servers, switches, routers, and storage equipment. RFID tags integrated into the optical fiber cable connectors and the adapters into which they fit can be used to accomplish this tracking automatically. For patch panel fields, the resulting density of RFID tags is very high, but by proper antenna design it is possible to read all 456 UHF RFID tags in a typical patch panel field with 6 dB power margin, even at densities as great as 4.2 tagged components per square inch of patch panel surface area.

Active and passive integration on flexible glass substrates: Subtractive single micron metal interposers and high performance IGZO thin film transistors

Flexible glass is one of the most promising innovations in the 21st century. Its applications in roll-to-roll (R2R) based manufacturing can yield low cost, conformable, and transparent electronics. In this work, we introduce electronic interposer substrates consisting of multiple metal-insulator layers of subtractively processed single micron metal circuit lines as well as high performance IGZO thin film transistors fabricated on Corning® Willow® Glass. All processes are compatible with R2R patterning and fabrication.

Ultra-Low Mass Planar SOFC Design

This work describes our early stage efforts to develop an ultra-low mass SOFC design based on a “frit-frame” approach where sealing and framing functions are integrated. Low mass, thermal shock tolerant SOFC systems are of interest for portable power application. Small systems based on microtublar cells have shown excellent cyclability in small systems, but scaling and cost remain issues. Planar designs have shown excellent scalability. Scalable low mass SOFC systems capable of rapid thermal cycling would be of particular interest for portable applications.

Reliability Assessment and Microstructure Characterization of Cu Pillars Assembled on Si and Glass Substrates

With the challenges of moving to 2.5/3D packaging structures, it has become imperative to improve our understanding of the materials science of fine pitch Pb-free solder joints. The use of Cu pillars capped with thin layers of SnAg solder provides for tighter bump pitches reducing the chance of solder bridging at chip joining. However, changes in geometry, materials and processes associated with 2.5 D packaging create new materials challenges. The thinner solder regions mean that a larger volume fraction of joints is consumed by the formation of intermetallic compounds at the pillar/SnAg solder interface. The final concentration of Ag in the joint can vary, and the Ag3Sn precipitate morphology in the solder joint may change, directly affecting the reliability of the joint. This can occur through the formation of Ag3Sn plates, or simply because of different distributions of much smaller Ag3Sn precipitates. Or, the entire solder joint may be transformed into intermetallic compounds during assembly or operation of fine pitch joints. The presence of interposer materials with a different CTE compared to FR-4 laminates may also affect the lifetime of the package during drop/shock or thermal fatigue. In the current study, relations between processing, microstructure and reliability of assemblies enabled through Cu pillar/interposer technology were examined. The effects of solder cap composition, thickness and volume on microstructure of assemblies on Si and glass substrates were examined. Effects of multiple reflows on the microstructure of solder joints were also studied. Significant variation in Ag3Sn precipitate morphology was observed under nominally identical fabrication conditions. These were correlated with relatively large variations in mechanical behavior, for instance in measured values of shear strength. Large variations in Ag3Sn precipitate size and number were also observed with changes in composition and upon aging, as would be expected. Cu pillar assemblies revealed small, but continuous solder layers. After failure during ATC, cracks were found to have propagated through these continuous solder layers.

Transparent Antennas for Wireless Systems Based on Patterned Indium Tin Oxide and Flexible Glass

Efficient antennas were achieved at 2.4 GHz and 5.8 GHz in which a transparent conductor, ITO, was deposited on only one side of the glass through sputtering. Antenna structures including grid, loop, and split ring monopoles were also designed and tested. An ITO layer of 650 nm was needed to consistently maintain a sheet resistance of 10 ohms/square or less to reduce antenna losses. A 100 nm aluminum doped silicon dioxide layer was deposited to buffer the ITO from the flexible glass to ensure high conductivity, and photolithography was used to define the antennas followed by an annealing process to improve the ITO conductivity and transparency. A packaging technique using 3D printed frames, Corning® GPPO connectors, and conducting epoxies yielded good antenna performance in terms of radiation efficiency and mismatch loss. Good agreement between simulations and measurements for packaged devices was obtained. Examples of antenna packaging, measurement results, and performance are presented.