Arif Sasongko

Mobile Tracking System Based on Event Driven Method

Monitoring system can be performed both offline and online, and this research carries out the design of long-distance monitoring system for moving system. GPS module is used as system input containing position information of monitored system. This information is processed by the system and is sent by GSM module. On the receiver side, the data are compiled for monitoring system movement. The system is implemented using µC Cortex-M4 by applying Event Driven method. This method is applied for saving resource. The result shows good accuracy level which is measured based on monitoring with system position in the field

Fast and reconfigurable packet classification engine in FPGA-based firewall

In data communication via internet, security is becoming one of the most influential aspects. One way to support it is by classifying and filtering ethernet packets within network devices. Packet classification is a fundamental task for network devices such as routers, firewalls, and intrusion detection systems. In this paper we present architecture of fast and reconfigurable Packet Classification Engine (PCE). This engine is used in FPGA-based firewall. Our PCE inspects multi-dimensional field of packet header sequentially based on tree-based algorithm. This algorithm simplifies overall system to a lower scale and leads to a more secure system. The PCE works with an adaptation of single cycle processor architecture in the system. Ethernet packet is examined with PCE based on Source IP Address, Destination IP Address, Source Port, Destination Port, and Protocol fields of the packet header. These are basic fields to know whether it is a dangerous or normal packet before inspecting the content. Using implementation of tree-based algorithm in the architecture, firewall rules are rebuilt into 24-bit sub-rules which are read as processor instruction in the inspection process. The inspection process is comparing one sub-rule with input field of header every clock cycle.

Transaction Level Modeling for Early Verification on Embedded System Design

Time-to-market pressure and productivity gap are two factors that encourage the Electronic Design Automation (EDA) industry and researcher of embedded system to enhanche embedded system design method. Current embedded system design approach, Register Transfer Level, is not sufficient to fulfill the embedded system design necessity. It needs a new design method above RTL, higher abstraction layer. Electronic System Level is general term that used to name system above RTL. ESL definition so far is a system above RTL including hardware and software. In this paper we designed a Transaction Level Modeling for early verification on embedded system design. This modeling is used to know functionality fulfillment at early stage. We specify four kind model for early verification purpose.

Simple power analysis attack against elliptic curve cryptography processor on FPGA implementation

The additional information (side effects) in Elliptic Curve Cryptography (ECC) hardware can be used to attack cryptographic systems. Additional information related to time, power consumption and electromagnetic radiation. Side channel attacks have been done with SPA (Simple Power Analysis), DPA (Differential Power Analysis), SEMA (Simple Electromagnetic Analysis) and DEMA (Differential Electromagnetic Analysis). Some scalar multiplication algorithm can be used to countermeasure SPA attack on elliptic curve cryptography. In this study, conducted experiments side-channel attacks ECC hardware implementations use binary algorithms by observing power consumption of ECC processor on FPGA. Experimental of side-channel attack is conducted to guess the secret key for data encryption and decryption by looking at the physical differences on hardware side effects. In this study, side-channel attack experimental is successful 100% get the key by analyzing of power consumption ECC processor.

On-board non-regression test of HLS tools targeting FPGA

High-Level Synthesis (HLS) has opened an opportunity for software programmers to target FPGA more rapidly. When developing HLS tools, tests are desirable to ensure their function, reliability and performance. When modifications are applied to a tool, Non- Regression Test (NRT) asserts that the changes have intended effect while Regression Test (RT) verifies that the tool still performs correctly without unwanted behaviour. The work presented in this paper is focused on a method to automatically perform Non-Regression Test in HLS tool developments, although it can also be used as a Regression Testing technique. This method relies on a framework which allows HLS tool developers to verify the circuits generated from the tool directly on FPGA, instead of using simulations. The verification flow is automatic, so that knowing the details of the system is unnecessary for developers. The framework has been tested successfully over several applications from HLS benchmark and it gives more promising results than its simulation counterpart.

Shortening SoC design time with new prototyping flow on reconfigurable platform

A modern SoC contains complex hardware components and a huge amount of software. These software parts, including the operating system, become so complex that their validation and debug is not feasible anymore by classical ISS based simulation approaches. Hardware prototypes are built to allow early software development and hardware-software integration. However the development of an application specific prototype takes a lot of time and effort. In this paper, we present an efficient approach for complex SoC prototyping on reconfigurable prototyping platform. This method provides all advantages of hardware prototyping solutions, but it avoids the time and cost required to build an application specific prototype.

Embedded application prototyping on a communication-restricted reconfigurable platform

As the complexity of SoC is increasing, prototyping becomes more and more suitable than simulation to validate the design. Reconfigurable platform is the solution to attain this prototyping in realistic cost and time. Unfortunately, most of the reconfigurable platforms have fixed communication network. This property becomes a restriction to implement the nowadays applications which have very complex and sophisticated communication network. In this paper, we present a novel approach for embedded application prototyping using reconfigurable platform under communication restriction. The effectiveness of our approach is illustrated through an application example using an ARM Integrator platform.

Towards SoC Validation Through Prototyping: A Systematic Approach Based on Reconfigurable Platform

Hardware/software covalidation is becoming one of the most critical issues in current System-on-Chip (SoC) design. Nowadays, covalidation is usually performed by cosimulation which is slow and lacks accuracy. The other alternative is to build a hardware prototype specific to the application. However, this alternative is expensive in terms of time, man-power, and cost. As SoCs increase in complexity, validation becomes more and more difficult, time consuming and error prone. Thus, a new approach for covalidation is inescapable.In this paper, we present a novel efficient prototyping approach for complex SoC covalidation. The proposed approach enables systematic prototyping of embedded applications on a reconfigurable platform. The process starts from the RT level model of the application. The application and the reconfigurable platform have to be adapted to obtain the prototype. We decompose the prototyping process into four steps, in order to match the application and the platform. Besides, we propose adapted solutions to deal with constraints typically encountered in existing reconfigurable platforms.The main advantages of this method are: fast and accurate validation, systematic prototyping flow, and large application field. Prototyping of a subset of VDSL using the ARM Integrator platform illustrates the effectiveness of our approach.

Prototyping dynamic task migration on heterogeneous reconfigurable systems

Reconfigurable devices, such as FPGAs, have been known to offer an excellent performance and a high efficiency in computation. Due to their improving capacity and more efficient architecture recently, there are growing interests in using FPGAs as coprocessors in reconfigurable systems. However, FPGAs still lack the support in dynamic scheduling, e.g. to manage multiple tasks or users in a system. Performing runtime task relocation or load distribution is not possible unless the reconfigurable system supports dynamic task migration. Such ability requires the automation of configuration and context management in reconfigurable architecture, which is not available in the existing solutions. In this paper, we propose a framework for prototyping dynamic task migration between heterogeneous FPGAs. A task running on one FPGA can be suspended and resumed on another FPGA with different architecture. The extraction and restoration of FPGA registers and memory values are possible due to the task-specific extraction mechanism provided by the tasks. The proposed framework exploits a high-performance embedded processor tightly-coupled to an FPGA to automatically manage the configuration and context. It utilizes two popular heterogeneous reconfigurable systems in the implementation, Xilinx Zynq ZC706 and Altera Arria V SoC. Tests are performed using graphical and non-graphical benchmark applications and performance results are presented.

Sibling relationship and block allocation table in file system for smart card operating system

Smart card operating system has main functions to manage command execution and manage files in memory. To facilitate the file management, a modest file system which has single rooted hierarchy is designed. Sibling relationship, which is a relation between child files under the same directory file, is used to make relation between files. This relation enables parent file to get connected with every child. Memory allocation which uses 1 byte addressing needs a large amount of memory. To reduce memory usage, addressing method with block allocation table (BAT) is used. Using BAT, memory is divided into three main parts: block allocation table which indicates the use of every blocks in memory, file table which contains information about file structure and file relation, and file body which contains information about file type, access condition, and actual data. There are three file types supported by this file system: transparent, fixed-length record, and variable-length record. This file system is tested using file management and file access command. The operating system is written in C language and implemented in FPGA-based smart card with 8051 processor.