Arihide Noda

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems

As 40Gb/s optical communication systems enter the commercial stage, the transceiver, which is a key component of these systems, requires lower power dissipation, a size reduction, and a wider frequency range to meet the requirements of several standards, such as OC-768/STM-256 (39.8Gb/s), OTU-3 (43.0Gb/s), and 4×10GbE-LANPHY (44.6Gb/s). 40Gb/s transceivers have already been reported in SiGe-based technology.However, they dissipate more than 10W in total and do not support 39.8-to-44.6Gb/s wide-range operations [1–2]. There have been recent reports on CMOS transceivers, but their speed performance is still less than 40Gb/s and their output signal suffers from large jitter [3–5]. In this paper, 40Gb/s SFI-5-compliant TX and RX chips in 65nm CMOS technology consume 2.8W each. This low power dissipation allows for a small and low-cost plastic BGA package. The TX has a full-rate clock architecture that is based on a 40GHz VCO, a 40Gb/s retiming D-FF, and 40GHz clock-distribution circuits that lead to a low jitter of 0.57psrms and 3.1pspp at 40Gb/s. A 40/20GHz clock-timing-adjustment circuit based on a phase interpolator is used to ensure wide-range error-free operations (BER ≪ 10−12) at 39.8 to 44.6Gb/s. A quadruple loop architecture is introduced in the CDR circuit of the RX, resulting in a 38Gb/s error-free operation (BER ≪ 10−12) at 231−1 PRBS with a low rms jitter of 210fs in the recovered clock.

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems

A fully integrated 40 Gb/s transmitter and receiver chipset with SFI-5 interface is implemented in a 65 nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides good jitter performance with a 40 GHz full-rate clock architecture that alleviates pattern-dependent jitter and eliminates duty cycle dependence. The measured RMS jitter on the output is 570 fs to 900 fs over the range of 39.8 Gb/s to 44.6 Gb/s with a 231-1 PRBS pattern. The receiver chip operates over the range of 37 Gb/s to 41 Gb/s. The measured RMS jitter on the recovered clock is 359 fs to 450 fs. By taking advantage of CMOS technology, each chip achieves low power consumption of 2.8 W and full integration of SFI-5 functions, PRBS generators/error checkers, a DPSK precoder/decoder, and control interfaces in a 4.9 × 5.2 mm2 die.

Compensation for PMD-induced time-variant waveform distortions in 43-Gbit/s NRZ transmission by ultra-wideband electrical equalizer module

We have successfully demonstrated error-free transmission of 43-Gbit/s NRZ WDM signals over a 405-km SMF having a maximum of 15.6-ps DGD with our newly-developed equalizer. The equalizer removes fatal BER-degradations from rapidly time-variant waveform distortions

112Gb/s optical transponder with PM-QPSK and coherent detection employing parallel FPGA-based real-time digital signal processing, FEC and 100GbE Ethernet interface

We demonstrate 112Gb/s transmission using PM-QPSK format and FPGA-based real-time digital signal processing. By employing framed processing architecture for polarization demultiplexing and carrier phase estimation, stable operation of error free after FEC and wide frequency offset have been achieved.

20Gbps/ch optical interconnection between SERDES devices over distances from chip-to-chip to rack-to-rack

20-Gbps signal transmission of up to 100 m between two SERDES devices has been demonstrated using newly developed driver and receiver ICs tuned to the characteristics of VCSELs, photodiodes, and electrical transmission line with which they are used.

Requirements for high-frequency LD FM response in an optical CPFSK heterodyne delay demodulation system

The required high-frequency laser diode (LD) FM responses for a continuous phase frequency shift keying (CPFSK) heterodyne delay modulation system were investigated. The degradations due to insufficient high-frequency FM response are evaluated, considering the FSK waveform distortion, which gives undesired phase error at the demodulation circuit. From the phase error, bit error rate (BER) degradation is calculated. The calculated results indicate that the delay-time adjustment for the demodulation circuit is effective in minimizing the power penalty. The theoretical evaluation, including the demodulation circuit optimization, explains the experimental results fairly well. Using the same evaluation procedure, required high-frequency LD FM responses are derived. The results, together with the required low-frequency FM responses, give guidelines for transmitter LD selection for coherent CPFSK systems. >

A 35-to-46-Gb/s Ultra-Low Jitter Clock and Data Recovery Circuit for Optical Fiber Transmission Systems

We demonstrated an ultra-low jitter clock and data recovery (CDR) circuit that covers an ultra wide frequency range from 35 Gb/s to 46 Gb/s. Our CDR has a newly developed dual input LC-VCO with a fine/coarse tuning scheme and a dual-loop architecture, which consists of a phase tracking loop and a frequency tracking loop. The CDR chip, which was made using an InP-HBT process, shows an extremely clear eye opening with an ultra-low jitter (< 9 mUI-rms) and an error-free operation (<1times10-12) throughout a wide range of 35 to 46 Gb/s at a 231-1 PRBS signal. The RMS and peak-to-peak jitter of the recovered clock were 226 fs and 1.56 ps, respectively. We suppressed output jitter to half of that found in previous work. In addition, a stable bit error rate (BER) that is insensitive to PRBS word length was demonstrated during an optical transmission test. These results show that our full-rate CDR is a very promising chip for 40-Gb/s-class optical transmission systems with the multi data rates.

Development of Alicyclic Polymers for Multimode Waveguide Array and its Characteristics for Use in Optical Interconnection

We have carried out elemental research and development regarding optical transmission technology to establish the petaFLOPS - (1015 floating point number operations per second) class supercomputer. We describe our development of an alicyclic polymer, waveguide arrays formed with the polymer, and their characteristics for multimode optical data transmission. We have also developed high-density optoelectronic modules with a 4.5times4.5times0.5-mm low-temperature co-fired ceramic (LTCC) substrate that transmits 12 signals, and demonstrated a 10-Gbps/ch error-free transmission with the polymeric-waveguide array. We also showed a 20-Gbps/ch optical eye as a transmitter with a 1.1-mum range InGaAs vertical-cavity surface-emitting laser (VCSEL).

A high accuracy channel power extraction method in optical filter-less coherent detection for flexible ROADM

We propose a novel channel power extraction method in optical filter-less coherent detection. By detecting amplitude of optimally filtered electrical analog waveform, we achieved optical channel power monitoring accuracy of ±1dB under actual operation condition.

Prototype of signal degradation monitor based on wavelength resolved Stokes vector analysis featuring a function of identification of the cause of degradation

We resolved signal degradations due to DGD and OSNR from a single monitor source. We verified a precision of +/−0.2dB of Q-value experimentally with a monitor prototype and 160Gb/s signal.