Arijit Mondal

Reasoning about timing behavior of digital circuits using symbolic event propagation and temporal logic

Present-day designers require deep reasoning methods to analyze circuit timing. This includes analysis of effects of dynamic behavior (like glitches) on critical paths, simultaneous switching, and identification of specific patterns and their timings. This paper proposes a novel approach that uses a combination of symbolic event propagation and temporal reasoning to extract timing properties of gate-level circuits. The formulation captures the complex situations like triggering of traditional false paths and simultaneous switching in a unified symbolic representation in addition to identifying false paths, critical paths, as well as conditions for such situations. This information is then represented as an event-time graph. A temporal logic on events is proposed that can be used to formulate a wide class of useful queries for various input scenarios. These include maximum/minimum delays, transition times, duration of patterns, etc. An algorithm is developed that retrieves answers to such queries from the event-time graph. A binary decision diagram-based implementation of this system has been made. Results on the International Symposium on Circuits and Systems (ISCAS)85 benchmarks are presented

A new approach to timing analysis using event propagation and temporal logic

Present day designers require deep reasoning methods to analyze circuit timing. This includes analysis of effects of dynamic behavior (like glitches) on critical paths, simultaneous switching and identification of specific patterns and their timings. This paper proposes a novel approach that uses a combination of symbolic event propagation and temporal reasoning to extract timing properties of gate-level circuits. The formulation captures complex situations like triggering of traditional false paths and simultaneous switching in a unified symbolic representation in addition to identifying false paths, critical paths as well as conditions for such situations. This information is then represented as an event-time graph. A simple temporal logic on events is proposed that can be used to formulate a wide class of useful queries for various input scenarios. These include maximum/minimum delays, transition times, duration of patterns, etc. An algorithm is developed that retrieves answers to such queries from the event-time graph. A complete BDD based implementation of this system has been made. Results on the ISCAS85 benchmarks indicate very interesting properties of these circuits.

Intelligent Scheduling of Thermostatic Devices for Efficient Energy Management in Smart Grid

Residential, commercial, and industrial buildings have been reported to consume a large portion of the generated energy. With the introduction of smart grid and its energy optimization techniques, it is now possible to efficiently manage and control consumers’ energy usage to fulfil their demands with the existing energy generation infrastructure, which otherwise seems to be a backbreaking challenge. This paper presents an efficient energy management solution for buildings with a large number of thermostatic devices (air conditioners) that maintain the temperature of different thermal zones in a predefined range. The primary objective of this paper is to schedule the thermostatic devices in order to reduce total energy consumption by these devices when they are in operation for a very long duration of time, while maintaining the other constraints. We formulate it as a graph problem where minimum mean cycle will provide the desired solution. The proposed methodology ensures that at no point in time the power consumption goes beyond a certain peak power consumption limit. We also enhance the methodology to reduce peak load consumption. Furthermore, a fast greedy approach has been developed to efficiently scale up the aforementioned scheduling scheme for a large number of devices. Experimental results show that significant improvements can be obtained by the proposed approaches over existing algorithms in reducing average energy consumption.

Real-time embedded systems analysis — From theory to practice

Summary form only given. Real-time embedded applications span a wide range of domains including automotive and flight control systems, monitoring systems, multimedia systems, virtual reality, interactive gaming, robotics, telecommunications, etc. A late response in these systems might cause a wrong behavior which could possibly even lead to a critical system failure. A typical example is an anti-lock braking system in a car that is required to release the brakes within (say) 60 milliseconds to prevent the wheels from locking. In most real-time systems design, the task / application scheduler is a major architectural component responsible for ensuring proper processing of all tasks having timeliness constraints on their execution response. In the presence of several concurrent activities running on a processor, the realtime scheduler has to ensure that each activity completes within its deadline. The first part of this tutorial introduces real-time embedded systems in general highlighting their key design issues and then presents a few important scheduling mechanisms employed on uni-processor and multiprocessor real-time systems. While scheduling strategies are directed towards handling the contention for CPUs among several real-time tasks, it cannot guarantee timing and performance constraints for the entire system in the presence of variable memory access and data communication times, actual execution path taken by the applications, the micro-architecture of the platform used etc. Validating timing and performance properties for these embedded real-time systems through system level timing analysis has evolved as a research theme in its own merit. In the second part of this discussion, we will present a systematic study of the developments in this area. The embedded real-systems under consideration are becoming increasingly complex. With an ensemble of complex components and diverse functionalities on board, the problem of verification for real time systems implementations is often turning out to be an insurmountable task. This fascinating theme has inspired decades of research on effective full-proof methods that can handle these diverse system types and prove properties on them. Verification models ranging from automata variants and hybrid formalisms have appeared in literature and several success stories have been reported. In this part, we will present a survey of this evolving landscape with a detailed discussion on some of the promising methods that have been put to real practice. Validation and test have been intensively studied and understood for hardware systems and software programs separately. However, embedded systems not only consist of hardware components, a large portion is realized by firmware and programs. The general concept of VLSI testing cannot be directly applied for embedded hardware because of the close interaction with the software components. Thus, all the steps for testing namely test planning, test pattern generation, DFT etc. needs to consider the fact that the hardware needs to be looked from the angle that it executes some software embedded in it. As most of the embedded systems in modern times involve real time constraints, the test and validation techniques need not only determine correct operation but also ensure that computations are completed within the given time lines. In the fourth part of the tutorial, we will discuss the challenges involved in testing and validation of real-time embedded systems and various evolving techniques to handle them.

Timing Analysis of Sequential Circuits Using Symbolic Event Propagation

Accurate timing information of circuits is essential for high quality designs. This paper presents a symbolic event propagation based method to determine the critical delay of digital circuits. The proposed approach considers the effect of glitches, multiple transitions and simultaneous switching on the critical delay. Our method identifies and eliminates both combinational and sequential false paths. We also consider triggering of traditional combinational false paths due to multiple transitions. The mathematical formulation makes no assumption about the start state of the finite state machine extracted from the sequential circuit. Few approximate methods have been proposed to determine the upper bound of the critical delay. A complete BDD based implementation has been made. Results on ISCAS89 benchmark circuits are presented

Multi-Objective Heuristic Charge Scheduling and Eco-Routing Mechanism for Electric Vehicles

We propose an efficient charge scheduling and routing mechanism for a set of electric vehicles with the objective to optimize average time and energy consumption for a tour. We propose a graph-based offline heuristic scheduling algorithm, whose performance evaluation is done in comparison to optimal results on graphs depicting real world scenario. Obtained preliminary results indicate that the proposed algorithm is highly efficient and effective in producing solutions that are significantly closer to optimal solutions.

Brownout Based Blackout Avoidance Strategies in Smart Grids

Power shortage is a serious issue especially in third world countries, and is traditionally handled through rolling blackouts. Today, smart grids provide the opportunity of avoiding complete blackouts by converting them to brownouts, which allow selective provisioning of power supply to support essential loads while curtailing supply to less critical loads. In this work, we formulate brownout based power distribution scheduling as an optimization problem and propose a modified Dynamic Programming (DP) based optimal algorithm (suitable for moderate sized grids) that is 9 to 40 times faster than the conventional DP approach.

Partitioned Fair Round Robin: A Fast and Accurate QoS Aware Scheduler for Embedded Systems

A large class of embedded systems today which concurrently execute numerous independent QoS sensitive applications like streaming audio and video, web browsing, email, interactive gaming etc. Have proportional share schedulers at their heart as the principal resource multiplexing strategy. However, producing schedulers that have both low scheduling overheads as well as good proportional share allocation accuracy have proved to be a daunting task. On one hand, we have schemes that provide optimal task allocation fairness accuracy, but generally suffer scheduling overheads that are at least logarithmic to the number of tasks. On the other hand there are O (1) complexity round-robin based algorithms, but they generally fail to provide good fairness properties. This paper presents Partitioned Proportional Round-Robin (PPRR), a two level hierarchical O (1) proportional share scheduler that achieves near optimal fairness accuracy while executing a mix of jobs with varying priorities in most practical scenarios. Simulation based experimental results reveal that even on systems containing up to 50 tasks with skewed execution rate requirements, a PPRR scheduler with just eight groups is able to provide less than about one percent deviation per task with respect to their ideal execution rates.

Performance optimization of real time control systems using variable time period

This paper presents a strategy for optimization of scheduling for a set of real time control tasks using variable time periods. We assume non-preemptive scheduling of the tasks. The time period for each task is selected in such a way so that the performance of the system is optimized. An offline assignment of periods using branch and bound based methodology is proposed to find an optimal schedule for the tasks. An interval scheduling scheme is presented to overcome the computational overhead of variable time period approach. We propose a greedy approach to solve this problem quickly. We present a comparative analysis of our approaches with traditional non-preemptive EDF scheduling. We observed that 30%-50% gain in overall performance for optimal solution and 10%-30% gain using greedy approach. The computation time for greedy approach is significantly small compared to branch and bound based method.

Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults

We present a symbolic-event-propagation-based scheme to generate hazard-free tests for robust path delay faults. This approach identifies all robustly testable paths in a circuit and the corresponding complete set of test vectors. We address the problem of finding a minimal set of test vectors that covers all robustly testable paths. We propose greedy and simulated-annealing-based algorithms to find the same. Results on ISCAS89 benchmark circuits show a considerable reduction in test vectors for covering all robustly testable paths.