Viduneth Ariyarathna

Multi-beam 4 GHz microwave apertures using current-mode DFT approximation on 65 nm CMOS

A current-mode CMOS design is proposed for realizing receive mode multi-beams in the analog domain using a novel DFT approximation. High-bandwidth CMOS RF transistors are employed in low-voltage current mirrors to achieve bandwidths exceeding 4 GHz with good beam fidelity. Current mirrors realize the coefficients of the considered DFT approximation, which take simple values in {0,±1,±2} only. This allows high bandwidths realizations using simple circuitry without needing phase-shifters or delays. The proposed design is used as a method to efficiently achieve spatial discrete Fourier transform operation across a ULA to obtain multiple simultaneous RF beams. An example using 1.2 V current-mode approximate DFT on 65 nm CMOS, with BSIM4 models from the RF kit, show potential operation up to 4 GHz with eight independent aperture beams.

Mixed microwave-digital and multi-rate approach for wideband beamforming applications using 2-D IIR beam filters and nested uniform linear arrays

The presented work explores novel methods for synthesizing approximately frequency independent array factors at lower hardware complexity for wideband beamforming applications. The proposed approach employs 2-D infinite impulse response (IIR) digital beam filters together with nested uniform linear arrays (ULAs). The array is designed to have multiple levels of nesting. Each level of nesting consists of a ULA covering a temporal subband of the incident wideband signal. The use of nested arrays provides the required aperture size using a smaller number of elements compared to using a single ULA to capture the entire wideband signal. The use of different levels of nesting allows the operation of the digital processor for each sub-band at different clock rates. This is a hierarchical approach that saves both digital VLSI hardware and power consumption. The 2-D IIR digital beam filters that process each subband signal from each of the nested subarray achieves wideband beamforming. Simulations illustrate approximately frequency independent passbands as required in wideband beamforming.

Wideband mixed microwave-digital 2-D IIR beam filters for nested uniform linear array processing

The synthesis of approximately frequency independent array factors at low hardware complexity using 2-D infinite impulse response (IIR) digital beam filters and nested uniform linear arrays is proposed. The array is designed to have multiple levels of nesting. Each level consists of a uniform linear array (ULA) covering a separate subband of the incident wideband signal. The use of nested arrays allows the required aperture size albeit using a significantly smaller number of elements compared to using a single ULA to capture the entire wideband signal. The use of different levels of nesting further allows the operation of the digital processor for each sub-band at different clock rates. This is a hierarchical approach which saves both digital VLSI hardware and power consumption. The 2-D IIR digital beam filters that process each subband signal from each of the nested subarray achieves wideband beamforming. Frequency domain simulations have been carried out to illustrate the concept of generating approximately frequency independent fan-shaped beam passbands as required in wideband beamforming.

A Parallel Method for the Computation of Matrix Exponential Based on Truncated Neumann Series

This paper introduces a new method for computing matrix exponential based on truncated Neumann series. The efficiency of the method is based on smart factorizations for evaluation of several Neumann series that can be done in parallel and divided across different processors with low communication overhead. A physical realization on FPGA is provided for proof-of-concept. The method is verified to be advantageous over the usual Horners rule approach for polynomial evaluation. The hardware verification shows a reduction of 62% in time required for processing for series approximations with 9 terms. Software verification demonstrates a 30% reduction in time compared to Horners rule and the trade-offs between using a higher precision approach is illustrated.

Design of a low-complexity wideband analog true-time-delay 5-beam array in 65nm CMOS

Non-squinting wideband analog multi-beamformer is proposed using true time delay (TTD) element delay Vandermonde matrix (DVM). Efficient realization of the DVM is achieved by sparse factorization, which leads to low-complexity hardware implementations (i.e. less number of delay blocks). It is shown that the proposed approach saves 36 TTD elements in a 5-beam multi-beamformer (4-beams corresponding to the 4-point DVM plus the direct sum beam) giving rise to a 60% reduction of hardware in the design compared to the direct implementation. Proposed low-complexity 5-beam multi-beamformer uses all-pass filters as the delay element and measured S-parameters from a fabricated 65 nm CMOS all-pass filter is used to compute the array patterns of the proposed design in the 1.6–2.4 GHz range.

Wideband delay-sum digital aperture using Thiran all-pass fractional delay filters

A delay-and-sum wideband beamforming architecture is proposed employing digital fractional delays realized via Thiran recursive all-pass filters. FIR filter based fractional delay approximation blocks that are used in standard delay-and-sum beamformers are replaced by Thiran all-pass fractional delay filters. Thiran filters - which are of IIR type - provide maximally flat group delay compared to other IIR fractional delay approximations. The digital hardware complexity for wideband beamformers is dominated by parallel multipliers in the signal processing system. Proposed wideband beamformer provides better performance in terms of the bandwidth and the flatness of the magnitude response, compared to FIR-filter based beamformers for a given level of digital hardware circuit complexity. It shows a 20% increase in the operational bandwidth compared to the method that calculates filter coefficients using the Lagrange interpolation. The proposed Thiran-filter based beamformer is realized on the ROACH-2 FPGA hardware platform for 16- and 8-element antenna arrays. A Xilinx Virtex-6 based FPGA prototype operates at a clock frequency of 357 MHz for full-band beamforming.