Armelle Bonenfant

Static Loop Bound Analysis of C Programs Based on Flow Analysis and Abstract Interpretation

One of the important steps in processing the worst case execution time (WCET) of a program is to determine the loops upper bounds. Such bounds are crucial when verifying real-time systems. In this paper, we propose a static loop bound analysis which associates flow analysis and abstract interpretation. It considers binary operators (+, -, *, \) for the loop increment, nested loops, non-recursive function calls, simple loop conditions (==, !=,, Gt=, &&) and loop upper bound values (instead of intervals). We present the result of our analysis on the Malardalen benchmark suite and compare them to the recent work of Ermedahl et al.

parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for high-performance with timing-predictable execution. parMERASA will provide a timing analyzable system of parallel hard real-time applications running on a scalable multicore processor. parMERASA goes one step beyond mixed criticality demands: It targets future complex control algorithms by parallelizing hard real-time programs to run on predictable multi-/many-core processors. We aim to achieve a breakthrough in techniques for parallelization of industrial hard real-time programs, provide hard real-time support in system software, WCET analysis and verification tools for multi-cores, and techniques for predictable multi-core designs with up to 64 cores.

WCET Analysis of a Parallel 3D Multigrid Solver Executed on the MERASA Multi-Core

To meet performance requirements as well as constraints on cost and power consumption, future embedded systems will be designed with multi-core processors. However, the question of timing analysability is raised with these architectures. In the MERASA project, a WCET-aware multicore processor has been designed with the appropriate system software. They both guarantee that the WCET of tasks running on dierent cores can be safely analyzed since their possible interactions can be bounded. Nevertheless, computing the WCET of a parallel application is still not straightforward and a high-level preliminary analysis of the communication and synchronization patterns must be performed. In this paper, we report on our experience in evaluating the WCET of a parallel 3D multigrid solver code and we propose lines for further research on this topic.

Worst-case execution times for a purely functional language

This paper provides guaranteed bounds on worst-case execution times for a strict, purely functional programming notation. Our approach involves combining time information obtained using a low-level commercial analyser with a high-level source-derived model to give worst-case execution time information. We validate our results using concrete timing information obtained using machine code fragments executing on a Renesas M32C/85 microcontroller development board. Our results confirm experimentally that our worst-case execution time model is a good predictor of execution times.

FFX: a portable WCET annotation language

In order to ensure safety of critical real-time systems it is crucial to verify their temporal properties. Such a property is the Worst-Case Execution Time (WCET), which is obtained by architecture-dependent timing analysis and architecture-independent flow fact analysis. In this article we present a WCET annotation language which is able to express such information originating from the user or the analysis. The open format, named FFX to stand for Flow Facts in XML, is portable, expandable and easy to write, understand and process. We argue that FFX allows to reuse and exchange the annotation files among WCET tools. FFX therefore permits to tighten WCET results and decreases the effort to support new architectures. Additionally, FFX flow fact files allow fair comparisons of both flow facts and WCET results. FFX can be used for quality assurance when developing new analysis techniques, using it as a flow fact database to test against. We present a small case study exemplifying the above points. Our case study puts special focus on the aspect of comparability and information exchange among WCET tools. In our experiments with FFX, we use the WCET analysis tool chains Otawa/oRange and r-TuBound/CalcWCET167.

Towards resource-certified software: a formal cost model for time and its application to an image-processing example

Visual tracking requires sophisticated algorithms working in real-time, and often space-limited, settings. While the input streams may be regular in structure, the algorithms are not, and must often deal with probabilistic metrics. To ensure progress in algorithm design without incurring excessive development costs, we propose a high-level programming approach married with predictable and compositional performance metrics. This enables the combination of independently developed program components into coherent software architecture, with certified resource use guarantee. Here, we present our approach and discuss its application to the development and resource analysis of a space bound mean shift algorithm for motion tracking, using the new embedded system-oriented language Hume.

Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore

The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore processor. A pattern-supported parallelization approach was developed to ease sequential to parallel program transformation based on parallel design patterns that are timing analyzable. The parallelization approach was applied to parallelize the following industrial hard real-time programs: 3D path planning and stereo navigation algorithms (Honeywell International s.r.o.), control algorithm for a dynamic compaction machine (BAUER Maschinen GmbH), and a diesel engine management system (DENSO AUTOMOTIVE Deutschland GmbH). This article focuses on the parallelization approach, experiences during parallelization with the applications, and quantitative results reached by simulation, by static WCET analysis with the OTAWA tool, and by measurement-based WCET analysis with the RapiTime tool.

Partial flow analysis with oRange

In order to ensure that timing constrains are met for a Real-Time Systems, a bound of the Worst-Case Execution Time (WCET) of each part of the system must be known. Current WCET computation methods are applied on whole programs which means that all the source code should be available. However, more and more, embedded software uses COTS (Components ...), often afforded only as a binary code. Partialisation is a way to solve this problem. In general, static WCET analysis uses upper bound on the number of loop iterations. oRange is our method and its associated tool which provide mainly loop bound values or equations and other flow facts information. In this article, we present how we can do partial flow analysis with oRange in order to obtain component partial results. These partial results can be used, in order to compute the flow analysis in the context of a full application. Additionally, we show that the partial analysis enables us to reduce the analysis time while introducing very little pessimism.

Identifying Relevant Parameters to Improve WCET Analysis

Highly-configurable systems usually depend on a large number of parameters imposed by both hardware and software configuration. Due to the pessimistic assumptions of WCET analysis, if left unspecified, they deteriorate the quality of WCET analysis. In such a case, supplying the WCET analyzer with additional information about parameters (a scenario), e.g. possible variable ranges or values, allows reducing WCET over-estimation, either by improving the estimate, or by validating the initial estimate for a specific configuration or mode of execution. Nevertheless, exhaustively specifying constraints on all parameters is usually infeasible and identifying relevant ones (i.e. those impacting the WCET) is difficult. To address this issue, we propose the branching statement analysis, which uses a source-based heuristic to compute branch weights and that aims at listing unbalanced conditionals that correspond to system parameters. The goal is to help system-experts identify and formulate concise scenarios about modes or configurations that have a positive impact on the quality of the WCET analysis.