Arthit Thongtak

Signal transition graph based logic synthesis for asynchronous control circuits using template based method

This paper proposes an approach for reducing additional signals in signal transition graph (STG) based logic synthesis for asynchronous control circuits. The proposed scheme introduces a template based method in state encoding process to insert additional signals to STG with a small number. According to our method, complete state coding (CSC) property can be satisfied without using state graph tracing which is used in classical state based method. Our method is useful for large scale asynchronous controllers, and also it can guarantee the other relevant properties, such as persistency and consistency. Our process begins with an encoding STG using Petri-net level in order to form a template STG. Then the projection to each non-input signals from an original STG is done. After that, we trace the projection to smaller state space. If the small state space shows conflicts, we have to insert balance signals from template STG. Unbalance signals are inserted after in case the space still shows conflicts. Finally, we can get the STG with appropriate insertion points which is used to be projected for CSC support on each non-input signals. Asynchronous DMA controller is an example of our proposed method. The final part of this paper is concluded with a complexity comparison between our template based method with state based method and structural encoding method. It shows that the number of iterative signal removal according to our method is less than others.

Distributed Lock Relation for Scalable-Delay-Insensitive Circuit Implementation Based on Signal Transition Graph Specification

Signal transition graph specification has a potential to describe behavior of hardware system in term of concurrent, sequential and one instance of the same events. One typical idea is for asynchronous control circuits, which is a variety of delay assumption design by means of signal transition graph specification. This paper proposes a distributed lock relation to determine the completion path for multiple-cycle signals. We select the tardy internal-completion signal to be the volunteer signal based on Scalable-Delay-Insensitive (SDI) model. The effectiveness of the proposed methodology is evaluated by cost of area, which is number of internal input signals and literal logic gates.

Digital scrum board using leap motion

In this paper, we propose an alternative option to digital scrum board using leap motion device. We apply a leap motion device to control and perform activities on digital scrum board for improving team communication during a daily meeting. It is more convenient way for the scrum team to present and control the digital scrum board, rather than using a mouse pointing device, especially during participating the stand-up meeting. Moreover, we propose a set of the hand motion patterns based on the basic leap motion gestures, in order to efficiently click and select, drag and drop, and scroll the elements of the digital scrum board. The time spent measurement experiments are conducted to demonstrate and provide the evidence of the better performance when the digital scrum board is equipped with the leap motion device and our hand motion patterns.

Translating Basic Metric Temporal Logic Formulas into Promela

To formally verify the real-time system using model checking technique, two necessary elements are required, the real-time system model and its expected real-time properties. In order to specify these real-time properties, an appropriate extended logic system, to cope with quantitative of time constraints is needed. We select one of the most popular real-time logic systems, called Metric Temporal Logic (MTL) to specify our mentioned real-time properties. However, the real-time properties defined in MTL are still not relevant to SPIN model checker. In this paper, we propose a novel scheme to translate the basic MTL formulas into Promela and LTL formulas as to be relevantly used in SPIN, in terms of Promela’s inline definitions and macro commands. The punctuality of the formulas is preserved during the translation. Practically, the basic timing constraints eventually and always operators of MTL are focused, and the translation of MTL formulas of the real-time safety property patterns is demonstrated.

A Design of Asynchronous Quasi‐Delay Insensitive Computer

This paper proposes the self‐timed circuit design. Quasi‐delay insensitive circuit is introduced as asynchronous prototype. The designed circuit focuses on asynchronous processor design. The processor employs asynchronous system bus, asynchronous DMA controller and synchronous interfaces. The system almost completely asynchrony operation except I/O devices and memory interfaces, due to a limitation on the present time devices, the designed has been implemented on spartan‐3E FPGA no. 3S500EFG320 by partitioning each module to prevent place and routing conflict, 100‐Mhz memory frequency connected, and consumes 141, 063 equivalent gate counts. Finally, the timing details of each instruction execution are shown.