Takashi Nanya

An equivalence checking methodology for hardware oriented C-based specifications

Verification to validate designs is one of the important tasks in VLSI design flow. Due to the great advances in integration, verification for whole designs is getting more and more difficult. To solve this problem in early stages of design flows, we suggest a formal equivalence checking method for given two C-based hardware oriented specifications (C descriptions). To verify large C descriptions efficiently, we use textual differences in the two C descriptions and verify them in terms, of symbolic simulation. We believe that our approach will be useful where two specifications to be verified are very close, which is a very common situation in practical designs.

Performance evaluation of Cascade ALU architecture for asynchronous super-scalar processors

Current out-of-order architectures have the critical path in the memory structure. Since the memory access delay mainly consists of wire delays, the feature size reduction will make little contribution to the critical path reduction. Therefore, the performance of the out-of-order architecture will not improve in spite of an expected advance in future technologies. To solve this problem, we present a novel architecture, called the Cascade ALU architecture, in which the critical path lies in the ALU. Since the ALU latency mainly consists of gate delays, the cycle time can be reduced with feature size reduction. In the Cascade ALU architecture, the instruction execution latency varies depending on executed instructions. Thus, an asynchronous implementation is suitable for the Cascade ALU. Since asynchronous handshake overhead may be too large to enhance the processor performance with the Cascade ALU, we show a method for hiding the handshake overhead, based on the fine-grain pipelining. Finally, we show the evaluation results that demonstrate the Cascade ALU architecture can achieve a good performance scalability in the ALU latency reduction.

Performance optimization of synchronous control units for datapaths with variable delay arithmetic units

Nowadays, variable delay arithmetic units have been used for implementing a datapath of a target system in pursuit of performance improvement. However, adoption of variable delay arithmetic units requires modification of a typical synchronous control unit design methodology. A telescopic arithmetic unit based methodology is one of representative methodologies to design synchronous control units for variable delay datapaths. In this paper, we propose two optimization methods for it. Proposed optimization techniques will be analyzed in order to show their performance improvement effects explicitly.

Generation and verification of timing constraints for fine-grain pipelined asynchronous data-path circuits

Timing analysis is a method for verification of timing constraints in a digital circuit. Asynchronous circuits bring new concerns for timing analysis with their local completion circuits, which generate cycles in the circuit and require special handling. In this paper constraints in fine grain pipelined asynchronous data-path circuits are examined in detail and a tool environment for automatic generation and verification of these constraints are presented along with some sample layout results.

A four-phase handshaking asynchronous controller specification style and its idle-phase optimization

A known problem of the four-phase handshaking protocol is that the signals involved in the handshake need to return to its initial state (a return-to-zero phase, also known as idle-phase) before starting another cycle, in which no useful work is usually done. In this paper we first define an easy-to-write specification style to specify four-phase handshaking asynchronous controllers that can be translated to an STG to obtain a gate-level implementation using existing synthesis methods. Then, we propose an algorithm that takes a controller specification written using our specification style and finds an optimized timing to start the idle-phase such that its gate level implementation has the idle-phase overhead reduced.

Control signal sharing using data-path delay information at control data flow graph descriptions

Due to the state explosion problem, signal transition graph based asynchronous circuit synthesis cannot handle large specifications. To overcome this problem, we propose two control signal sharing methods by using the delay information of data-path circuit. Since the number of states is exponential with the number of signals in the synthesis, the reduction of signals by sharing can reduce the number of states in exponential order. They are carried out at the control of data path operations which is represented as a control flow graph description, without sacrificing the critical path delay of the data-path circuit. Experimental results are encouraging in that a number of control signals can be shared by our methods.

Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units

In order to enjoy the performance improvement effects of variable computation time arithmetic units at a system level, we propose a new synchronous control unit design methodology for dataflow graphs under allocation of a telescopic arithmetic unit, which is one of the well-known synchronous variable computation time arithmetic units. The proposed method generates an independent synchronous controller for each component arithmetic unit, and builds a distributed synchronous control unit through integrating the derived controllers. The distributed structure of the final synchronous control unit maximizes the performance improvement effect of telescopic arithmetic units through a complete preservation of original concurrency among operations.

Logic optimization for asynchronous speed independent controllers using transduction method

Asynchronous speed independent (Sl) circuits based on an unbounded gate delay model often suffer from high area penalty. It happens due to the lack of efficient global optimization. This paper presents a boolean optimization method based on tranduction method to optimize asynchronous Sl circuits while preserving hazard-freeness.