Arthur D. Friedman

Fault Detection in Redundant Circuits

It is shown that a set of diagnostic tests designed for a redundant circuit under the single-fault assumption is not necessarily a valid test set if a fault occurrence is preceded by the occurrence of some (undetectable) redundant faults. This is an additional reason (besides economy) for trying to eliminate certain kinds of redundancy from the circuit. However, single-fault analysis may remain valid for some types of redundancy which serve a useful purpose, such as the elimination of logic hazards in two-level circuits.

Fault Detection in Iterative Logic Arrays

Kautz has studied the problem of testing one-and two-dimensional arrays of combinational cells under the assumptions that all cell inputs must be applied to a cell to test it completely and that a fault in a cell may cause any arbitrary change in its outputs. In this paper we study the same problem under a more restricted set of assumptions: 1) all faults in a cell can be detected by a known set of inputs (usually smaller than the set of all inputs); and 2) each fault will affect the cell outputs in a known manner. Necessary and sufficient conditions for detection of faults in one-dimensional arrays are obtained. A procedure for deriving efficient tests for one-dimensional arrays is presented. Sufficient conditions for the testability of two-dimensional arrays and procedures for constructing tests for some arrays are obtained.

Feedback in Synchronous Sequential Switching Circuits

In this paper we consider minimum feedback loop realizations of synchronous sequential switching circuits. It is shown that any finite state sequential function can be realized as a synchronous sequential circuit with a single feedback loop, or equivalently, as a one-dimensional iterative circuit with one amplifier between stages. Techniques are described which enable us to find such a realization for a given flow table. A simple test procedure is described to determine if a sequential function can be realized as a sequential circuit using its output function as feedback, whether the output is completely or incompletely specified.

Feedback in Asynchronous Sequential Circuits

In this paper we attempt to realize any flow table of a desired sequential circuit so as to minimize the feedback index (number of feedback loops) of the resulting asynchronous sequential switching circuit. It is shown that any flow table M, which describes the circuit action of a normal fundamental mode asynchronous sequential circuit, can be realized as a fundamental mode circuit with feedback index [log 2 S], where S is the maximum number of stable states in any input column of M. The realization requires no inverters (assuming double rail inputs) and thus can be shown to be a minimum transistor, as well as a minimal feedback index, realization for any transistor-diode circuit realization of M. Nonfundamental mode realizations of normal mode flow tables are also considered, and it is shown that such a realization can be found with only one feedback loop, assuming ideal inertial delays, for any given flow table. However, no ideal inertial delay realization has been discovered which does not contain internal feedback. Finally, minimum feedback realizations of non-normal and nonfundamental mode flow tables are briefly considered.

Feedback in asynchronous sequential circuits

In this paper we examine the problem of feedback in asynchronous sequential circuits. A procedure is presented whereby any normal fundamental mode flow table can be realized as a fundamental mode circuit with feedback index ⌈log2maxi(Si)⌉ where Si is the number of stable states in column i of the flow table and it is shown that this result is optimal. The realization requires no inverters (assuming double-rail inputs), and is therefore a minimal transistor realization if diode logic is used.

Synthesis of asynchronous sequential circuits with minimum number of delay elements

In this paper, we present a procedure for realizing any normal mode flow table by an asynchronous sequential circuit with a single pure delay, so that no hazards are present even if several input variables change in a transition. A modification of Ungers single delay realization is also proposed in order to allow several inputs to change in a transition without producing output transients. We also show how any normal mode flow table can be realized without inserted delay elements if a restriction on the relative magnitudes of line and gate delays is satisfied and only one input variable is allowed to change in a transition.

Comments on "Design of Diagnosable Iterative Arrays"

This correspondence shows that, contrary to a statement in the cited paper, fault location is sometimes possible in one-dimensional arrays in which only the outputs of the rightmost cell are observable.

R70-17 Asynchronous Sequential Circuits with Feedback

In the design of synchronous sequential machines, various canonical realizations which make use of feedback shift registers have been developed oped [1], [2]. This paper attempts to extend some of these results to realize asynchronous machines in a similar manner.

Universal single transition time asynchronous state assignments

In this paper we consider the problem of deriving general bounds on the number of state variables required to realize an asynchronous flow table as a function of n, the number of states of the flow table for Single Transition Time (STT) assignments in which all variables which must change in a given transition are allowed to change simultaneously in a noncritical race.