Premachandran R. Menon

Synthesis of delay-verifiable combinational circuits

We address the problem of testing circuits for temporal correctness. A circuit is considered delay-verifiable if its timing correctness can be established by applying delay tests. It is shown that verifying the timing of a circuit may require tests which can detect the simultaneous presence of more than one path delay fault. We provide a general framework for examining delay-verifiability by introducing a special class of faults called primitive path delay faults. It is necessary and sufficient to test every fault in this class to ensure the temporal correctness of combinational circuits. Based on this result, we develop a synthesis procedure for combinational circuits that can be tested for correct timing. Experimental data show that such implementations usually require less area than completely delay testable implementations. >

Design of Asynchronous Circuits Assuming Unbounded Gate Delays

This paper considers the general problem of the synthesis of asynchronous combinational and sequential circuits based on the assumption that gate delays may be unbounded and that line delays are suitably constrained. Certain problems inherent to circuit realizations with unbounded gate delays are discussed and methods of solving them are proposed. Specific synthesis techniques are presented for both combinational and sequential circuits. The use of completion detection necessitated by the assumption of unbounded gate delays also causes the circuits to stop operating for approximately half of all possible single faults, thus achieving a degree of self-checking.

Fault Detection in Iterative Logic Arrays

Kautz has studied the problem of testing one-and two-dimensional arrays of combinational cells under the assumptions that all cell inputs must be applied to a cell to test it completely and that a fault in a cell may cause any arbitrary change in its outputs. In this paper we study the same problem under a more restricted set of assumptions: 1) all faults in a cell can be detected by a known set of inputs (usually smaller than the set of all inputs); and 2) each fault will affect the cell outputs in a known manner. Necessary and sufficient conditions for detection of faults in one-dimensional arrays are obtained. A procedure for deriving efficient tests for one-dimensional arrays is presented. Sufficient conditions for the testability of two-dimensional arrays and procedures for constructing tests for some arrays are obtained.

BIST-based delay path testing in FPGA architectures

The widespread use of field programmable gate arrays (FPGAs) as components in high-performance systems has increased the significance of path delay faults in FPGAs. We present a technique for FPGA path delay fault detection which integrates test insertion with the FPGA placement and routing stages to accomplish testing with low test application time. An accurate static timing analyzer is used to identify critical paths and built-in self-test (BIST) hardware is inserted using a placement and routing tool. Initial experimental results show that testing is accomplished with low test application time for several benchmark designs.

Symbolic test generation for hierarchically modeled digital systems

The authors present a symbolic test generation algorithm which uses a hierarchical model of the data path and a finite state model of the control section of the system under test. The data path may contain sequential modules, as well as synchronous feedback loops. The stable table of the control section can be used by the test generation algorithm to generate test even in complex sequential modes of operation of the system. The symbolic approach presented is applicable with a top-down, as well as a bottom-up, approach to hierarchical test generation. With a top-down approach, symbolic constraints derived at a higher level are used in deriving module tests, thereby guaranteeing that the tests will be applicable in the environment in which the module is used. If a bottom-up approach is used, tests for any module in its operating environment are obtained by combining symbolic tests and module tests.<<ETX>>

An approach to functional level testability analysis

The authors present an approach to testability analysis applicable to circuits containing functional modules described behaviorally. They consider two types of modules-combinational modules described by binary decision diagrams and sequential modules defined by state tables. Controllability and observability measures for such modules are defined, and algorithms are developed for computing them. The method has been applied to a few small modules and circuits, and appears to be feasible. The combinational measures, applicable to both combinational and sequential modules, indicate the probability of setting a lead to a particular value or observing the effect of a signal change at an output. The sequential measures, also applicable to both types of modules, give estimates of sequence lengths needed for controlling and observing any lead in the circuit. These two measures together give an indication of not only the difficulty in deriving tests for a circuit but also the length of test sequences that may be needed.<<ETX>>

SCRIPT: a critical path tracing algorithm for synchronous sequential circuits

The basic critical path tracing method for combinational circuits is outlined, and it is shown how it can produce pessimistic results in certain cases where fault effects propagate along multiple paths. The problem of extending the critical path tracing method to sequential circuits is considered. It is shown that the pessimistic nature of critical path tracing in combinational circuits may lead to optimistic results in sequential circuits, and a modification of the critical path tracing method to make it exact for combinational circuits is proposed. Based on this modification, a critical path tracing algorithm for synchronous sequential circuits is developed which is also exact. >

Realization of Asynchronous Sequential Circuits Without Inserted Delay Elements

Abstract—In an earlier paper, Unger showed that any normal mode flow table can be realized by an asynchronous sequential circuit without inserted delays in the feedback paths if and only if the flow table contains no essential hazards. No restrictions were placed on the relative magnitudes of line and gate delays. In this paper, we show that if the line delays are less than the minimum gate delay in the circuit, any normal mode sequential function can be realized without inserted delays. It is also shown that a weaker line delay assumption is sufficient. Two procedures for realizing asynchronous sequential circuits without inserted delays are presented.

Fault simulation on reconfigurable hardware

The authors introduce a new approach to fault simulation, using reconfigurable hardware to implement a critical path tracing algorithm. The performance estimate shows that the approach is at least on order of magnitude faster than serial fault emulation used in prior work.

Critical path tracing in sequential circuits

Critical path tracing has been shown to be faster than traditional fault simulation methods, but it produces pessimistic results in some cases involving reconvergent fanout. It is shown that the pessimistic nature of critical path tracing in combinational circuits can lead to incorrect results that are not necessarily pessimistic in sequential circuits. A modification of the method for removing the approximation is proposed, and a critical path tracing algorithm for synchronous sequential circuits is presented.<<ETX>>