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Arthur Peters

Honeywell

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Archive | 1989

Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing

George J. Barlow; Elmer W. Carroll; James W. Keeley; Wallace A. Martland; Victor M. Morganti; Arthur Peters; Richard C. Zelley

Archive | 1980

Local bus interface for controlling information transfers between units in a central subsystem

Arthur Peters; Virendra S. Negi; David E. Cushing; Richard P. Brown; Thomas F. Joyce

Archive | 1985

FIFO buffer to cache memory

Arthur Peters

Archive | 1980

Odd/even bank structure for a cache memory

Philip E. Stanley; Richard P. Brown; Arthur Peters

Archive | 1980

Data steering logic for the output of a cache memory having an odd/even bank structure

Arthur Peters; Philip E. Stanley

Archive | 1979

Arithmetic logic apparatus for a data processing system

Virendra S. Negi; Arthur Peters

Archive | 1980

Hit/miss logic for a cache memory

William E. Woods; Arthur Peters

Archive | 1980

Self-evaluation system for determining the operational integrity of a data processing system

Elmer W. Carroll; Virendra S. Negi; Arthur Peters

Archive | 1980

Diagnostic subsystem for a cache memory

Richard P. Brown; George J. Barlow; Arthur Peters

Archive | 1979

Control store address generation logic for a data processing system

Arthur Peters; Virendra S. Negi

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Virendra S. Negi

Honeywell

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Richard P. Brown

Honeywell

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Elmer W. Carroll

Honeywell

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George J. Barlow

Honeywell

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James W. Keeley

Honeywell

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David E. Cushing

Honeywell

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Philip E. Stanley

Honeywell

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Thomas F. Joyce

Honeywell

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Victor M. Morganti

Honeywell

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Chester M. Nibby

Honeywell

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