James W. Keeley

Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization

Resilient bus system

Recovery method and apparatus for a pipelined processing unit of a multiprocessor system

Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement

Multilevel cache system with graceful degradation capability

Shared interface apparatus for testing the memory sections of a cache unit

Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing

Cache resiliency in processing a variety of address faults

Read in process memory apparatus

Enable/disable control checking apparatus