Arthur Sheiman

A Reconfigurable Computing System Based on a Cache-Coherent Fabric

Typical reconfigurable computing systems are based on an I/O interconnect such as PCIe. This yields good bandwidth performance, but incurs significant overhead for small packet sizes, and makes the implementation of on-streaming-data applications unduly difficult. We describe an architecture based on Intel R Quick Path Interconnect R that addresses these concerns.

An FPGA Based Hybrid Processor Emulation Platform

This paper introduces a flexible, hybrid emulation platform for processor related emulation. It is based on a modern Xeon server and FPGA. With Intel processors implemented in FPGA and plugged into the Xeon servers processor socket, and with the Xeon BIOS modified to accommodate different cores, this platform is able to boot OS and run applications while interacting with the Xeon servers native hardware components. It enables researchers to do architectural changes in FPGA and quickly evaluate their effect on the whole platform. This platform is an ideal vehicle for research on processor technology, SoC architecture, reconfigurable computing, heterogeneous core architecture, etc.