Neal Oliver

Performance Evaluation of the 802.16 Medium Access Control Layer

In this work we investigate performance of the medium access control layer of an 802.16 wireless network consisting of 100 subscriber stations (SSs) and a single base stati on (BS). Experimental results show that the average packet queuing delay was virtually the same for weighted round robin and weighted fair queuing scheduling algorithms. Another interesting finding is that adapting the uplink/downlink ratio plays a crucial role in performance as the network load increases and channel conditions change. On the other hand, experiments show that for a higher network load, segmentation of large packets is a necessity in order to achieve performance and QoS conformance. We also observed a smaller average queuing delay for smaller values of frame duration.

A Reconfigurable Computing System Based on a Cache-Coherent Fabric

Typical reconfigurable computing systems are based on an I/O interconnect such as PCIe. This yields good bandwidth performance, but incurs significant overhead for small packet sizes, and makes the implementation of on-streaming-data applications unduly difficult. We describe an architecture based on Intel R Quick Path Interconnect R that addresses these concerns.

Performance Analysis of Packet Encapsulation and Aggregation

In an attempt to increase data throughput, many modern data transmission protocols provide capabilities for aggregating transmitted data fragments into larger packets at the time of encapsulation in a particular OSI layer. The decision and ability to aggregate packets into a single frame can have significant impact on the performance of the communication system. The impact can be even more substantial when the system operates under a heavy load. In this paper, we present a queuing model which describes a packet encapsulation and aggregation process. We assume Poisson arrivals and phase-type service time distributions for the transmitted packets. Using the proposed queuing model, we provide analysis of the end-to-end delay of a packet transmitted by the system. We verify analytical results with a simulation model of the system. Based on results of experiments with the analytical model, we provide the maximum number of packets in a single frame for which packet aggregation minimizes the average total delay of a packet for various system loads and sizes of the packet header. It is numerically shown that when the load is high, the higher the variability of the packet service time, the higher the maximum allowed number of packets in the frame should be to achieve the minimum average total packet delay. On the other hand, the impact of the variability of the packet service time is insignificant when the system load is moderate or low.

The limits of architectural abstraction in network function virtualization

Network Function Virtualization (NFV) is the paradigm of implementing network services as a network of functions on top of commodity off-the-shelf (COTS) servers. It is of profound interest to telecommunications network operators because of the promise of bringing the economics of data centers into the network. However, existing CPU, memory, and network interface architectures cause network service performance to be sensitive both to the implementation of individual network functions, but also to their placement within an NFV platform. For this reason, emerging NFV standards will confront the challenge of exposing certain platform architectural parameters to enable services to be orchestrated in an effective manner. The goal of the paper is to show that underlying technologies must be exposed to the Orchestrator during service deployment as incorrect placement can have a very significant impact on performance. We illustrate this by describing a “proof-of-concept” implementation of Quality of Service (QoS) for a Broadband Remote Access Service (BRAS)/Border Network Gateway (BNG). Our work focuses on studying performance implications related to PCIe bandwidth constraints, Virtual Network Function (VNF) placement, message buffer (mbuf) size and memory channel utilization.

A model of a packet aggregation system

The decision and ability to aggregate packets can have significant impact on the performance of a communication system. The impact can be even more substantial when the system operates under a heavy load. In this paper, we present a queuing model which describes a packet encapsulation and aggregation process. Using this model, we provide analysis of the end-to-end delay of a packet transmitted by the system. The analytical model is verified by a simulation model of the system. We calculate the maximum number of packets in a single frame for which packet aggregation minimizes the average total delay of a packet. It is numerically shown that when the load is high, the higher the variability of the packet service time, the higher the maximum allowed number of packets in the frame should be to achieve the minimum average total packet delay. However, the impact of the variability of the packet service time is insignificant when the system load is moderate or low.

Performance Analysis of Packet Schedulers in High-Speed Serial Switches

In this work we examine the performance of arbitration algorithms for core high-speed serial switches (HSSS). Taking Infiniband as an example, experimental results show that, for a homogeneous network load, the average queuing delay for the switch output ports under the weighted round-robin (WRR) algorithm defined for InfiniBand is similar to the average queuing delay resulting from the largest delay-first (LDF) or first-in-first-out (FIFO) algorithms. For a 4-port switch, when the average load is high (close to 95% of the network capacity) and unbalanced with respect to the WRR weights, the difference in average delay between WRR and LDF or FIFO is large. However, for a 20-port switch and the same high unbalanced average network load, this difference is less than half of that of the 4-port switch. Further, the average queuing delay difference between WRR and LDF or FIFO diminishes quickly as the average load decreases. Hence, even for a fairly high average load, LDF or FIFO can be suggested for arbitration in core HSSS.