Arthur van Roermund

Wireless Body Area Networks

The main design challenge for sensor nodes used in a WBAN is a low power consumption. System level aspects play an important role in the overall power consumption of body area networks. In this chapter different sensor network aspects and reported WBAN applications are analyzed and summarized. Additionally, several MAC protocols are compared using the WBAN properties. Since low power consumption is of primary importance, the sensor node energy consumption of the different MAC-layers are compared. With the energy consumption models, the solution space is examined. At the end of the chapter the receiver requirements are obtained.

Look-Ahead Based Sigma-Delta Modulation

The aim of this book is to expand and improve upon the existing knowledge on discrete-time 1-bit look-ahead sigma-delta modulation in general, and to come to a solution for the above mentioned specific issues arising from 1-bit sigma-delta modulation for SA-CD. In order to achieve this objective an analysis is made of the possibilities for improving the performance of digital noise-shaping look-ahead solutions. On the basis of the insights obtained from the analysis, several novel generic 1-bit look-ahead solutions that improve upon the state-of-the-art will be derived and their performance will be evaluated and compared. Finally, all the insights are combined with the knowledge of the SA-CD lossless data compression algorithm to come to a specifically for SA-CD optimized look-ahead design.

21.2 A 3nW signal-acquisition IC integrating an amplifier with 2.1 NEF and a 1.5fJ/conv-step ADC

Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively wearable autonomous sensors, large sensor arrays, or wireless self-powered sensors, require a minuscule form factor and very low power consumption. For example, the power available from a state-of-the-art 1mm3 solid-state thin-film battery is limited to 4nWfora 10yr lifetime [1], and a 1mm3 energy harvester attached to a running person delivers only 7.4nW [2]. While several low-power signal acquisition systems have been proposed [3-5], their consumption is still in the 20-to-1000nW range. Circuits aiming at low absolute power often result in low power-efficiency (due to overhead), high PVT sensitivity and poor reliability (due to the use of simplistic circuitry). This work presents a fully-integrated signal acquisition IC with six-fold lower power consumption than prior art, which provides state-of-the-art power-efficiency and ensures enough circuit reliability, precision and bandwidth to enable practical applications.

A 14b 200MS/s DAC with SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping

A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented. Compared to traditional static-mismatch mapping and dynamic element matching, DMM reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty. This 0.14µm CMOS DAC achieves a state-of-the-art performance of SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band.

30.4 A 13.56MHz RFID tag with active envelope detection in an organic complementary TFT technology

In the last several years, organic electronics have gained increasing consideration as a cost-effective alternative to silicon, especially in RFID applications. An inductive-coupled organic RFID operating at 13.56MHz was demonstrated on foil using p-type organic technologies [1]. A complementary organic technology was used for a 13.56MHz transponder in [2]. Recently, a complementary hybrid organic/metal-oxide process was exploited to demonstrate bidirectional communication in an HF RFID [3]. It adopts passive envelope detection using traditional diode-based schemes with OOK modulation. However, OOK modulation usually reduces sensitivity and reading range. In this work, a complementary organic TFT (C-OTFT) technology [4] is used for the first time to implement a 13.56MHz RX front-end, which exploits an active detection scheme and is able to demodulate ASK PWM-coded signals with modulation depth (h) as low as 25%.

A Wideband RF Mixing-DAC Achieving IMD < -82 dBc Up to 1.9 GHz

This paper presents a highly linear wideband Mixing-DAC architecture. A current-steering DAC core and a mixer are co-integrated at a unit current-cell level. A 1 bit DAC output stage is cascoded by a 1 bit mixer to form the Mixing-DAC current cell. An array of such current cells and a system front-end construct the Mixing-DAC. The system front-end includes digital signal processing and data synchronization, global LO driver and sort-and-combine calibration hardware. To reach high linearity, various techniques are used: digital dither, self measurement and calibration of amplitude and timing errors, local advanced cascoding scheme, bleeding currents, segmentation and accurate scaling of the LSB binary current cells. The proposed approach is validated by a 65 nm CMOS test-chip of a dual 16 bit 2 GS/s 4 GHz Mixing-DAC with IMD <; -82 dBc up to 1.9 GHz and output noise lower than -165 dBm/Hz.

A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme

This paper presents a 3.5 GS/s 6-bit current-steering digital-to-analog converter (DAC) with auxiliary circuitry to assist testing in a 1 V digital 28-nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035 mm2, making it suitable to embedding in VLSI systems, e.g., field-programmable gate array (FPGA). To cope with the IC process variability, a unit element approach is generally employed. The three most significant bit (MSBs) are implemented as seven unary D/A cells and the three least significant bits (LSBs) as three binary D/A cells, using appropriately reduced number of unit elements. Furthermore, all digital gates only make use of two basic unit blocks: a buffer and a multiplexer. For testing, a memory block of 5 kb is placed on-chip, which is externally loaded in a serial way but internally read in an 8× time-interleaved way. The memory is organized around 48 clocked 104-bit shift-registers. It keeps the resulting switching disturbances signal-independent and hence avoids inducing output nonlinearity errors, even when a common power supply is shared with the DAC. This novelty allows reliable testing of the DAC core, while avoiding performance limitation risks of handling high-speed off-chip data streams. The DAC Spurious Free Dyanmic Range >40 dB bandwidth is 0.8 GHz, while the IM3 <;-40 dB bandwidth exceeds 1.3 GHz. The DAC consumes 53 mW of power and the design-for-test scheme -80 mW.

15.4 A 0.8V 10b 80kS/s SAR ADC with duty-cycled reference generation

Autonomous wireless sensor nodes need low-power low-speed ADCs to digitize the sensed signal. State-of-art SAR ADCs can accomplish this goal with high power-efficiency (<;10fJ/conversion-step) [1-4]. The reference voltage design is critical for the ADC performance to obtain good PSRR, low line-sensitivity and a stable supply-independent full-scale range. However, solutions for efficient reference voltage generators (RVGs) are typically ignored in low-power ADC publications. In reality, due to the low power supply (usually sub-1 V) and limited available power (nW-range), the RVG is a challenge within the sensor system. In this work, a 2.4fJ/conversion-step SAR ADC with integrated reference is implemented. The 0.62V CMOS RVG consumes 25nW. To further reduce RVG power, it can be duty-cycled down to 10% with no loss in ADC performance. Additionally, the ADC uses a bidirectional dynamic comparator to improve the power efficiency even more.

A 62 GHz inductor-peaked rectifier with 7% efficiency

This paper presents the first 62 GHz fully onchip RF-DC rectifier in 65nm CMOS technology. The rectifier is the bottleneck in realizing on-chip wireless power receivers. In this paper, efficiency problems of the mm-wave rectifier are discussed and the inductor-peaked rectifier structure is proposed and realized. By using an inductor-peaked diode connected transistor, self-threshold voltage modulation, and an output filter, the measured rectifier reaches 7% efficiency with 1 mA current load. Compared to previous state-of-art 45 GHz rectifier with 1.2% efficiency [1], our solution achieves a higher efficiency at a higher frequency, providing a better solution for mm-wave wireless power receivers.

Adaptive RF front-ends for hand-held applications

The RF front-end – antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. Adaptive RF Front-Ends for Hand-Held Applications presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control, and adaptive power control. Several adaptive impedance control techniques are discussed, using a priori knowledge on matching network properties, in order to simplify robust 2-dimensional control. A generic protection concept is presented, based on adaptive power control, which improves the ruggedness of a power amplifier or preserves its linearity under extremes. It comprises over-voltage, over-temperature, and under-voltage protection.