Hans Hegt

A high performance license plate recognition system

This paper presents a powerful automated license plate recognition system, which is able to read license numbers of cars, even under circumstances, which are far from ideal. In a real-life test, the percentage of rejected plates was 13%, whereas 0.4% of the plates were misclassified. Suggestions for further improvements are given.

An on-chip self-calibration method for current mismatch in D/A converters

This paper presents an on-chip low-power self-calibration apparatus implemented in a 12-bit current-steering 250nm CMOS DAC. The DAC core consists of a noncalibrated binary LSB part and a calibrated thermometer MSB part. The thermometer currents are generated by combining a coarse 10-bit accurate current with a fine calibrating current provided by a small calibrating DAC (CALDAC). The magnitude of the fine current is determined in the digital domain and optimized for overall post-calibration accuracy. This digital process acquires mismatch error information from on an on-chip single bit ADC. The whole calibration process is executed once at chip power-up and the calibration results are recorded. During the normal operation of the DAC, no active calibration operations are present and the fine currents are kept static, so that the advantages of calibration are maintained even at very high conversion rates. The self-calibrated DAC achieves 12-bit static and dynamic linearity, while occupying smaller silicon area due to the intrinsic 10-bit accuracy of the DAC core.

Design of high-performance asynchronous sigma delta modulators with a binary quantizer with hysteresis

This work describes the design of asynchronous sigma delta modulators (ASDMs) with a binary quantizer with hysteresis. The ASDM is treated as a closed loop non-linear system that operates using an inherent limit cycle. A first and a second order ASDM have been implemented in a digital 0.18 /spl mu/m CMOS technology. The measured SFDR is 75 dB in a frequency band of 8 MHz for the first-order and 72 dB in a band of 12 MHz for the second-order ASDM.

A 14b 200MS/s DAC with SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping

A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented. Compared to traditional static-mismatch mapping and dynamic element matching, DMM reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty. This 0.14µm CMOS DAC achieves a state-of-the-art performance of SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band.

An 8MHz, 72 dB SFDR Asynchronous Sigma-Delta Modulator with 1.5mW power dissipation

An Asynchronous Sigma-Delta Modulator (ASDM) that achieves a SFDR of 72 dB with a bandwidth of 8 MHz is presented. The ASDM operates as a closed-loop, nonlinear system. Spectral analysis of the ASDM shows that a center frequency of at least 100 MHz is required for these specifications. Circuit implementations are presented and a prototype ASDM is realized in a digital 0.18 micrometer, 1.8V CMOS technology. The ASDM dissipates 1.5mW and has an area of 0.026mm/sup 2/.

On the stability of high order Sigma-Delta modulators

In this paper we present an approach for stability analysis of high order Sigma-Delta modulators. The approach is based on a parallel decomposition of the modulator. In this representation, the general N-th order modulator is transformed into decomposition of low order modulators, which interact only through the quantizer function. In the simplest case of the loop filter transfer function with real distinct poles, the low order modulators are N first order ones. The decomposition considered helps to extract the stability conditions of the N-th order modulator. They are determined by the stability conditions of each of the low order modulators but shifted with respect to the origin of the quantizer function, because of the influence of all other low order modulators. The approach is generalized for the case of repeated poles of the loop filter transfer function.

Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption

This paper describes a method for analysis and design of MOS voltage-to-current converters (V-I converters or transconductors) and introduces a novel V-I converter circuit with significantly improved linearity performance. The proposed method uses harmonic compensation for the linearization of the V-I characteristics and introduces a normalized representation of the converter equations. The analysis is applied for several circuit topologies based on MOS differential pairs. The circuits are compared with respect to their current consumption, signal to noise ratio, achievable linearity and bandwidth. The minimum required current consumption for certain linearity and dynamic range is derived. The proposed novel V-I converter circuit uses a combination of local resistive feedback and cross-coupling. In this way, it achieves significant, simultaneous suppression of the third and the fifth order harmonic components in the transconductor output current. The implementation constraints and the performance of the new circuit solution are evaluated via simulations on transistor level. A standard digital 0.18 micrometer, 1.8V, CMOS process is used.

A 62dB SFDR, 500MSPS, 15mW Open-Loop Track-and-Hold Circuit

In this work, the design of an open-loop front-end track & hold (T&H) circuit is considered. Advantages of the presented circuit include low power-consumption, high-speed operation, simple reliable design, and ability to operate at low power-supplies. The major problem of open-loop circuits is their relatively poor linearity. In the presented design, high linearity is achieved by applying three linearization techniques: clock boosting (Abo and Gray, 1999), resistive source degeneration (Razavi, 2001), (Ouzounov et al., 2005) and cross-coupling (Ouzounov et al., 2005), (Voorman and Veenstra, 2000). As a result, a linearity corresponding to 10-bit accuracy is achieved. The final design in a 0.18mum CMOS process achieves an SFDR of 62 dB using a sample frequency of 500 MHz while consuming 15mW at a 1.8V power supply

An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals

This paper presents an 11b 1GS/s ADC with a parallel sampling architecture to enhance SNDR for broadband multi-carrier signals. It contains two 1GS/s 11b sub-ADCs each achieving > 54dB SNDR for input frequencies up to Nyquist frequency and state-of-the-art linearity performance. The SNDR of the ADC with the parallel sampling architecture is improved by 5dB compared to its sub-ADCs when digitizing multi-carrier signals with large crest factors. This improvement is achieved at less than half the cost in power and area compared to the conventional approach. The chip is implemented in 65nm LP CMOS and consumes in total 350mW at 1GS/s.

A flexible 12-bit self-calibrated quad-core current-steering DAC

This paper presents a flexible fully integrated self-calibrated quad-core 12-bit current-steering 180 nm CMOS DAC. Its novel architecture features multiple parallel sub-DAC unit cores. Their various combinations deliver smart flexibility in: performance, functionality, power management, design reuse, and smartness. The parallel sub-DAC units can be used together or separately to optimize the performance of a targeted mixed-signal application. Unused sub-DAC units can be switched off to optimize the power consumption. The new parallel sub-DACs architecture facilitates a new calibration algorithm. This algorithm together with small calibrating DACs and a current comparator enables the realization of the first fully integrated self-calibration start-up method that corrects the mismatch errors of all binary and unary current sources. The presented self-calibrated flexible DAC achieves measured linearity of better than 12-bit, while occupying small silicon area due to the intrinsic 9-bit accuracy of the DAC unit core.