Arti Noor

An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop

In this paper, a single edge-triggered, static D flip-flop design suitable, for low power and low area requirements is proposed. Advantageously, the flip-flop is realized using only ten transistors. The flip-flop is implemented using Master-Slave configuration and can be used for lower cost memory and microprocessor chips. The 0.6-micron technology is used to implement the design and the area and power results were compared with existing SET D FFs. Simulation results indicated that the circuit is capable of significant power savings.

Intelligent Humidity Sensor for Wireless Sensor Network Agricultural Application

Wireless Sensor Networks (WSN) is now widely used in precision agriculture applications. Sensors play an important role in WSN. The traditional humidity sensors employed in the agriculture have a drawback that they acquire a large amount of data which is to be transmitted or processed. Whereas the intelligent sensor proposed in this paper uses a conventional sensor and an embedded processor that can process the data acquired using algorithms to reduce the amount of data collected, to extract only relevant information and to present this information in a format which minimizes post-processing latency. As a result of which the final processing end has to perform a little computation that too only on features (like significant changes in humidity) rather on the huge data hence reducing the power consumption. The intelligent humidity sensor reduces the amount of data processed by 50% (depending upon humidity variations) and thereby also reducing the power consumption.

CPL-Adiabatic Gated logic (CPLAG) XOR gate

In this paper authors have investigated the appropriateness of adiabatic circuit design techniques aiming to reduce the power dissipation by the VLSI circuits. Authors have implemented/proposed CPL based Adiabatic Gated (CPLAG) XOR gate which can be synchronized with the reference clock signal. The implemented CPLAG XOR gate is analyzed for different voltage levels for the capacitance involved with the power dissipation. The circuit is also analyzed for different temperature gradients for its functional and operational robustness in different operating conditions. The circuit operation is also tested to resetting the output node and associated power data. The implemented CPLAG based XOR gate has minimum dissipated power of 3.52×10-11W at 1v and maximum power of 6.10×10-10W at 5v. The power clock path offers maximum capacitance 1.40×1010F contributing 22% of the total circuit capacitance. From the power delay product it is found that the circuit best performs at 2v across different temperature ranges. After rigorous testing the circuit is found to be functionally successful.

Modified CPL Adiabatic Gated Logic - MCPLAG based DPET DFF with XOR

The use of Adiabatic Logic in VLSI chip design has certainly promised positive aspects in terms of optimizing the power equations. In the reported work authors have extended their proposed CPLAG based ‘XOR’ implementation. The modified ‘XOR’ implementation is further configured to implement a dynamic positive edge triggered D flip flop. Both the reported circuits are functionally verified and found to be satisfactory to a high degree of signal integrity and accuracy. DFF circuit is further examined with different load, temperature range, transistor size and voltage levels. The results obtained from the proposed implementation of hybrid ‘XOR’ and DFF have showed good results. The average power at 1.5V, 180nm, 25C, 1fF load is 0.209nW and 2339nW for 0.8v, 40C for different run with Pclk_Q delay 0.2ns, input_Q delay 16μs, Qtrise 44.6μs, Qtfall 61μs, Qbtrise 4.54μs, Qbtfall 3μs with 50.9 zepto units PDP. The average power consumption for a conventional semi-adiabatic PFAL DFF is 35mW approx as compared to 0.1μW for the implemented DFF. General Terms Low Power, VlSI Design, CPL, Adiabatic Logic. Power delay product, fully adiabatic logic, semi adiabatic logic

Design of Ternary Content Addressable Memory (TCAM) with 180 nm

This paper deals with the design and analysis of Ternary Content Addressable Memory using 180nm technology. The main aim of the TCAM is to perform the search operation using match line (ML). Ternary content addressable memories (TCAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of TCAMs, high power consumption is one of the most critical challenges faced by TCAM designers. TCAMs are popular because of their searching operation based on the content unlike the RAM cell which does it on the basis of address. The main contribution of this work is testing of ML. The testing of match line was a task which needs to be done to check the searching condition in the TCAM cell. To accomplish this task a new circuitry was added to the existing circuit in order to test the masking condition in a TCAM cell. The work was started from the scratch. First a RAM cell was designed with the goal in mind to be used for the TCAM cell. Various parameters were calculated for the stability of a SRAM cell. The SRAM cell designed was then used in the design of Binary CAMs. After the completion of binary CAM, the cell was modified into the TCAM cell. The additional circuitry added was used to test the working of match line during the search operation of the TCAM cell. Finally, design and testing of a complete TCAM cell is presented.

Reconfigurable CPL Adiabatic Gated Logic -RCPLAG based Universal NAND/NOR Gate

In precursory efforts authors have illustriously consolidated the benefits of CPL based circuits and adiabatic logic conjoint the use of clock for even combinational blocks and reported the power diminution. With the adhibition of clock in combinational blocks, the same circuit topology may be employed for sequential behavior as manifested by authors in their erstwhile works. Proceeding forward in the same direction and augmenting another edge into this, authors have reported the reconfigurable circuit implementation utilizing the reported CPLAG concepts. In pursuance of the same authors have contemplated and implemented reconfigurable ‘Nand’ and ‘Nor’ gates. The same circuit topology can be used for either functionality governed by a control signal. The functional behavior of the circuit realized for ‘Nand’ and ‘Nor’ are analyzed and found to be cogent. The power results shows improvement by 4-5% as compared to SCMOS based circuits. The proposed RCPLAG universal gate is investigated for different voltage levels and transistor size. The parameters like power dissipation, power fed back to system, Trise, Tfall, propagation delays, PDP are further examined and found to be satisfactory. The best operating conditions for the said circuit lies in voltage range of less than 2.5V. The Pavg at 1V, 180nm technology is 12.2nW with 36f units PDP, 5μs maximum delay. General Terms Low Power, VLSI Design, CPL, Adiabatic Logic. Power delay product, fully adiabatic logic, semi adiabatic logic

Deep sub-micron SRAM design for low leakage

This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power consumption and propagation delay. Initially the existing SRAM architectures are investigated, and thereafter a suitable basic 6T SRAM structure is chosen. The key to low power dissipation in the SRAM data path is to reduce the signal swings on the highly capacitive nodes like the bit and data lines. While designing the SRAM, techniques such as circuit partitioning, divide word line and low power layout methodologies are reviewed to minimize the power dissipation.

Design of a humidity sensor with PVT variations using AMI C5 CMOS technology

Humidity sensor can be defined as a device, which consists of plastic material whose characteristics change as per the amount of humidity present in the air. Its various application areas include controlling of the climate, storage of food articles, domestic applications etc. The reference paper implemented the humidity sensor uses post-CMOS processing of CMOS fabricated chips to obtain suspended and thermally isolated diodes. However, the paper does not include the read out circuit and the design of op-amp. Industry however always considers the design under PVT (process, voltage & temperature) variations to make it commercial. This paper aims in designing op-amp, which is used in the read out circuit of the CMOS humidity sensor based on PVT variation (process, voltage and temperature variation). The design issues for switch capacitor used in the humidity sensor are also described. The thermal design equations for the sensor diode model have also been considered and presented.

ISO 9001:2015 implementation in the e-learning based virtual teaching program

“Total quality management is a journey, not a destination.” ∼Berry. Success of a system comes from the satisfaction of the user and efficiency of the product. ISO 9001 is a quality management system, which explicitly focuses to achieve worth of a system through its guidelines and set of generic requirements. The outcome or end result of the quality audit differs based on the different programs, environments, services intended and target audience however the requirements and practices to accomplish the task remains the same. Assurance of proficient application and contentment to the end user is objective of the e-Learning based “Virtual Teaching program in Medical Sciences and health services”, being developed and implemented by CDAC, Noida for the benefit of the medical students of the two medical colleges-North Eastern Indira Gandhi Regional Institute of Health & Medical Sciences(NEIGRIHMS), Shillong & Regional Institute of Medical Sciences(RIMS), Imphal. The e-Learning program on which ISO 9001:2015 is applied is a first of the kind endeavor in the medical field with e-courses designed and delivered in the area of health & medical education. To ensure the delivery of quality in e-Learning courses through Virtual Teaching (V.T), compliance of the program, as per the ISO 9001:2015 quality standards were tested and successfully implemented. Various processes including Risk estimation, Project Management Plan(PMP), Effort estimation etc. for the quality assurance of the program were documented and implemented. After a series of internal & external audits, the program was qualified and conformed as the ISO 9001:2015 standard certified program. The major learning of this achievement was preparation of overall processes which focuses on the high quality and competent product development and delivery. This paper provides the details of the processes developed for achieving the ISO 9001:2015 certification and how the achievement benefitted in the program in enhancing the overall quality of the virtual teaching. The paper also proposes possible standard based application of the ISO 9001:2015 processes in various e-Learning programs for assured quality managed services & processes.

A secure and simplified technique for configuaring SRAM based FPGA

FPGAs are becoming increasingly attractive - thanks to the improvement of their capacities and their performances. Today, FPGAs represent an efficient design solution for numerous embedded solutions. There are several alternatives for configuring these FPGAs. However, these configuration solutions are vulnerable and often require significant up-front design effort and time. This paper proposes a simple, efficient and secure configuration method that utilizes a USB to SPI bridge chip to configure an FPGA device. This solution offers multiple benefits compared to traditional scheme where a microprocessor or microcontroller is used for the same. The approach considerably reduces component count, board space, and costs. The technique describes a low power and low cost dedicated interface for In-system programming of FPGA devices. This method can also serve to replace the popular JTAG configuration interface and eliminate the need for a separate JTAG connector on the board, hence reducing cost and board space moreover leading to more secure configuration. The design had been implemented and tested on a custom Xilinx FPGAs board.