Brajesh Kumar Kaushik

Organic Thin Film Transistors: Structures, Models, Materials, Fabrication, and Applications: A Review

Organic thin film transistor (OTFT) based device modeling and circuit application is a rapidly emerging research area. Taking cognizance of this fact, our paper reviews various basic to advanced OTFT structures, their performance parameters, materials of individual OTFT layers, their molecular structures, OTFT charge transport phenomena, and fabrication techniques. The performance of p- and n-type conducting polymer and small molecule organic semiconductors are reviewed primarily in terms of field effect mobility, current on/off ratio, and operating voltage for various OTFT structures. Moreover, different organic/inorganic materials for realizing the dielectric layer, electrodes, and the substrate in an OTFT are analyzed. Some of the compact models that are essential for predicting and optimizing the device performance are described that takes into account the mobility enhancement factor and channel length modulation. A detailed study of the single gate, dual gate, vertical channel, and cylindrical gate OTFT structures is carried out. Furthermore, the paper discusses some of the interesting and upcoming applications of organic transistors such as inverters, light emitting diodes (LEDs), RFID tags, and DNA sensors. Although organic transistors boast of a bright future with a wide spectrum of applications, but they still face several challenges in terms of mobility, voltage swings, noise margins, sub-threshold slope, stability, etc., that needs to be resolved to make them a commercially sustainable and viable technology.

Perspectives and challenges for organic thin film transistors: materials, devices, processes and applications

This paper reviews recent advancements in the field of organic electronics. Performance of p- and n-type conducting polymers and small molecule organic semiconductors is presented primarily in terms of mobility and current on/off ratio. Moreover, it presents a deep insight into different organic/inorganic materials used for the dielectric layer, electrodes and substrate for thin film transistors (TFTs). The electrical characteristics and performance parameters of single and dual gate structures are compared. In addition, performance dependence of organic TFT (OTFT) is discussed on the basis of contact resistance, channel length and thickness of the active layer. The paper thoroughly discusses several important applications of OTFTs including inverter, organic static random access memory, radio frequency identification tag and DNA sensors. It also includes several limitations and future prospects of organic electronics technology.

Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects

This paper deals in crosstalk analysis of a CMOS-gate-driven capacitively and inductively coupled interconnect. Alpha power-law model of a MOS transistor is used to represent a CMOS driver. This is combined with a transmission-line-based coupled-interconnect model to develop a composite driver-interconnect-load model for analytical purposes. On this basis, a transient analysis of crosstalk noise is carried out. Comparison of the analytical results with SPICE extracted results shows that the average error involved in estimating noise peak and their time of occurrence is less than 7%.

High-Performance and Robust SRAM Cell Based on Asymmetric Dual-

This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET) structure using a dual- k spacer. Asymmetric dual-spacer at source shows excellent gate control over the channel due to increase in the outer fringe field at gate/source underlap. Hence, this structure exhibits a superior short-channel effect metric over the conventional/single-spacer underlap FinFET. The proposed asymmetric structure enhances static random access memories (SRAMs) performance in terms of robustness, access times as well as leakage power during the hold, read, and write operations. The hold static noise margin and write margin increases by 5.16% and 5.66%, respectively. The read stability enhances by 13.75% and 19.35% over conventional FinFET SRAM circuit. Furthermore, the leakage power reduces by 60%, and write access time improves by 23.63%. Compared with conventional FinFET-based SRAM, same bit-cell area and read delay are associated with the proposed structure. Supply voltage scalability on SRAM design metrics is also investigated. In addition to SRAM application, underlap length, lateral source/drain doping gradient, and the high- k spacer width are optimized for high-performance digital applications.

k

This research paper analyzes, finite element based two dimensional device simulations for top and bottom contact organic field effect transistors (OFETs) by considering uniform and non-consistent mobility regions. To model the morphological disorder in bottom contact structure, some calibrated standards for simulation is developed viz. by considering variable low mobility regions near the contacts. An analytical model is developed, by considering contact resistance and field dependent mobility. The effect of channel length variation (5-40@mm) on performance parameters is highlighted for both the structures. Subsequently, results shows only 1% change in current for bottom contact with 0.5@mm and 1@mm low mobility region near the contacts, due to dominant contact resistance, whereas, linear dependency is observed for other simulated structures. The top contact device shows 0.43cm^2/Vs saturation mobility at 5@mm and 13% decrease up to 20@mm and afterwards constant behavior is noticed, whereas low mobility is extracted in bottom contact devices and shows 10-20% increase in both the mobilities for increasing channel length from 5 to 40@mm. For top and bottom devices, total 65% and 62% decrease in contact resistance is observed for increasing gate voltage from -1.8V to -3V and this percentage reduces for increasing the length of low mobility region. Further, we have evaluated 13%, 40% and 78% increase in the trap density, while proceeding for 0.25@mm, 0.5@mm and 1@mm low mobility region in the bottom contact structure.

Spacer FinFETs

Multiwalled carbon nanotube (MWCNT) and bundled single-walled carbon nanotube (SWCNT) interconnect have provided potentially attractive solution in current deep submicrometer and nanoscale technology. This letter presents a comparative analysis between the MWCNT and the bundled SWCNT at different global interconnect lengths in terms of crosstalk-induced time delay and area by using a three-line-bus architecture. Each line of the bus architecture is replaced by the RLC models of the MWCNT and bundled-SWCNT interconnects. The crosstalk-induced time delay is predicted at the middle line (victim) when the other two lines (aggressors) are switched in the opposite direction. From HSPICE circuit simulation results, it has been observed that the overall improvement in the delay is 52.4% more for the MWCNT as compared with the equivalent bundled-SWCNT interconnects. Consequently, on an average, the MWCNT requires 97.8% lesser area as compared with the bundled-SWCNT interconnects for the same crosstalk-induced time delay.

Channel length variation effect on performance parameters of organic field effect transistors

This paper accurately models the crosstalk effects in a CMOS-gate-driven coupled RLC interconnects using the nth power law model and finite-difference time-domain (FDTD) technique. The propagation delay, peak crosstalk voltage, and peak voltage timing on victim line of coupled-multiple lines are observed and compared to HSPICE simulation results for the global interconnect length at 32 nm technology node. The numerical results illustrate that the proposed model accurately estimates the performance parameters of driver interconnect load system. An average error of less than 2% is observed in estimation of peak crosstalk voltage and its timing. The proposed model can be extended for coupled n lines and useful for the evaluation of signal integrity, issues of EMI, and EMC of on-chip interconnects.

Analysis of MWCNT and Bundled SWCNT Interconnects: Impact on Crosstalk and Area

During recent years, high-k spacer materials have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance that restricts researchers using these devices in high-performance circuits. For the first time, this paper demonstrates the usage of high-k spacer material with an optimized length for effective reduction of circuit delay and an improvement in robustness. An improvised symmetric dual-k spacer (SymD-k) underlap trigate FinFET architecture termed as SymD-k is employed for this purpose. From extensive 3-D simulations, this paper demonstrates that SymD-k device significantly improves overall circuit delay and robustness (noise-margins) with fully capturing the fringe capacitance effects. A CMOS inverter and a three-stage ring-oscillator (RO3) are adopted to carefully investigate the performances. In comparison with the conventional device, the SymD-k device speeds up the RO3 circuit by 27% and 33% using high-k spacer dielectric HfO2 and TiO2, respectively. However, a purely high-k FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effect of underlap length and supply voltage on SymD-k-based RO3 delay over the conventional ones are also dealt in.

An Accurate FDTD Model for Crosstalk Analysis of CMOS-Gate-Driven Coupled RLC Interconnects

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent @p-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.

Investigation of Symmetric Dual-k Spacer Trigate FinFETs From Delay Perspective

Mixed carbon nanotube bundles (MCBs) are considered to be highly potential interconnect solutions in the current nanoscale regime. Different MCBs with random and spatial arrangements are proposed based on the placements of single- and multiwalled carbon nanotubes (CNTs) (SWNTs and MWNTs) in a bundle. Propagation delay and dynamic crosstalk performances are analyzed using the modified equivalent single conductor model of proposed MCB topologies. Encouragingly, a significant reduction in propagation delay and crosstalk delay is observed for a spatial arrangement of an MCB wherein MWNTs are placed peripherally to the centrally located SWNTs. Typically, the average delay with and without crosstalk is improved by 82.8% and 80%, respectively, compared to the MCB having randomly distributed SWNTs and MWNTs.