Arun Paidimarri

A 120nW 18.5kHz RC oscillator with comparator offset cancellation for ±0.25% temperature stability

Integrated low-frequency oscillators can replace crystal oscillators as sleep-mode timers to reduce the size and cost of wireless sensors [1]. Since the timer is one of the few continuously functioning circuits, minimizing its power consumption can greatly reduce sleep-mode power of highly duty-cycled systems. Temperature stability of the oscillator is important in order to minimize timing uncertainly and guard time for the radios, and thus maximizing sleep time. The voltage-averaging feedback method described in [2] achieves high stability in the MHz frequencies, but when scaled to the kHz range, requires very large filters. On the other extreme, gate leakage-based timers have been designed for sub-nW power consumption, but operate in the sub-Hz frequencies [3]. In the past, high accuracy RC oscillators in the kHz range have been designed with feed-forward correction [1] and self-chopped operation [4]. In this work, an offset cancellation architecture achieves long-term frequency stability and temperature stability while operating at lower power.

A 2.4 GHz Multi-Channel FBAR-based Transmitter With an Integrated Pulse-Shaping Power Amplifier

A 2.4 GHz TX in 65 nm CMOS defines three channels using three high-Q FBARs and supports OOK, BPSK and MSK. The oscillators have -132 dBc/Hz phase noise at 1 MHz offset, and are multiplexed to an efficient resonant buffer. Optimized for low output power ≈ - 10 dBm, a fully-integrated PA implements 7.5 dB dynamic output power range using a dynamic impedance transformation network, and is used for amplitude pulse-shaping. Peak PA efficiency is 44.4% and peak TX efficiency is 33%. The entire TX consumes 440 pJ/bit at 1 Mb/s.

Experimental study of the interplay of channel and network coding in low power sensor applications

In this paper, we evaluate the performance of random linear network coding (RLNC) in low data rate indoor sensor applications operating in the ISM frequency band. We also investigate the results of its synergy with forward error correction (FEC) codes at the PHY-layer in a joint channel-network coding (JCNC) scheme. RLNC is an emerging coding technique which can be used as a packet-level erasure code, usually implemented at the network layer, which increases data reliability against channel fading and severe interference, while FEC codes are mainly used for correction of random bit errors within a received packet. The hostile wireless environment that low power sensors usually operate in, with significant interference from nearby networks, motivates us to consider a joint coding scheme and examine the applicability of RLNC as an erasure code in such a coding structure. Our analysis and experiments are performed using a custom low power sensor node, which integrates on-chip a low-power 2.4 GHz transmitter and an accelerator implementing a multi-rate convolutional code and RLNC, in a typical office environment. According to measurement results, RLNC of code rate 4/8 can provide an effective SNR improvement of about 3.4 dB, outperforming a PHY-layer FEC code of the same code rate, at a PER of 10-2. In addition, RLNC performs very well when used in conjunction with a PHY-layer FEC code as a JCNC scheme, offering an overall coding gain of 5.6 dB.

Ultra Low-Energy Relaxation Oscillator With 230 fJ/cycle Efficiency

An ultra low-energy oscillator circuit is presented for use in picowatt level systems. The core oscillator uses an 18 transistor 3 stage architecture designed to minimize short circuit current. In addition, a transistor threshold is used to set the trip point as opposed to a voltage reference and comparator scheme, leading to overall energy savings. While operating across a wide range of low frequencies from 18 to 1000 Hz, the oscillator core consumes 110 fJ/cycle at 0.6 V. The circuit is demonstrated alongside an integrated current source to set the reference frequency. The combined system consumes a total power of 4.2 pW at 18 Hz, resulting in 230 fJ/cycle at 0.6 V.

An RC Oscillator With Comparator Offset Cancellation

A fully-integrated 18.5 kHz RC time-constant-based oscillator is designed in 65 nm CMOS for sleep-mode timers in wireless sensors. A comparator offset cancellation scheme achieves 4× to 25× temperature stability improvement, leading to an accuracy of ±0.18% to ±0.55% over -40 to 90 °C. Sub-threshold operation and low-swing oscillations result in ultra-low power consumption of 130 nW. The architecture also provides timing noise suppression, leading to 10× reduction in long-term Allan deviation. It is measured to have a stability of 20 ppm or better for measurement intervals over 0.5 s. The oscillator also has a fast startup-time, with the period settling in 4 cycles.

Small-Area, Resistive Volatile Organic Compound (VOC) Sensors Using Metal–Polymer Hybrid Film Based on Oxidative Chemical Vapor Deposition (oCVD)

We report a novel room temperature methanol sensor comprised of gold nanoparticles covalently attached to the surface of conducting copolymer films. The copolymer films are synthesized by oxidative chemical vapor deposition (oCVD), allowing substrate-independent deposition, good polymer conductivity and stability. Two different oCVD copolymers are examined: poly(3,4-ethylenedioxythiophene-co-thiophene-3-aceticacid)[poly(EDOT-co-TAA)] and poly(3,4-ehylenedioxythiophene-co-thiophene-3-ethanol)[poly(EDOT-co-3-TE)]. Covalent attachment of gold nanoparticles to the functional groups of the oCVD films results in a hybrid system with efficient sensing response to methanol. The response of the poly(EDOT-co-TAA)/Au devices is found to be superior to that of the other copolymer, confirming the importance of the linker molecules (4-aminothiophenol) in the sensing behavior. Selectivity of the sensor to methanol over n-pentane, acetone, and toluene is demonstrated. Direct fabrication on a printed circuit board (PCB) is achieved, resulting in an improved electrical contact of the organic resistor to the metal circuitry and thus enhanced sensing properties. The simplicity and low fabrication cost of the resistive element, mild working temperature, together with its compatibility with PCB substrates pave the way for its straightforward integration into electronic devices, such as wireless sensor networks.

Multi-channel 180pJ/b 2.4GHz FBAR-based receiver

A three-channel 2.4GHz OOK receiver is designed in 65nm CMOS and leverages MEMS to enable multiple sub-channels of operation within a band at a very low energy per received bit. The receive chain features an LNA/mixer architecture that efficiently multiplexes signal pathways without degrading the quality factor of the resonators. The single-balanced mixer and ultra-low power ring oscillator convert the signal to IF, where it is efficiently amplified to enable envelope detection. The receiver consumes a total of 180pJ/b from a 0.7V supply while achieving a BER=10-3 sensitivity of -67dBm at a 1Mb/s data rate.

13.7 A +10dBm 2.4GHz transmitter with sub-400pW leakage and 43.7% system efficiency

In this paper, a 2.4GHz BLE-compatible transmitter architecture for use in ultra-low-duty-cycle applications has been presented. Low-voltage operation, extensive power gating and a negative-gate-biasing technique help in achieving a peak TX efficiency of 43.7% at an output power of +10.9dBm while also reaching a leakage power of 370pW, for an on/off ratio of 7.6×107.

A 440pJ/bit 1Mb/s 2.4GHz multi-channel FBAR-based TX and an integrated pulse-shaping PA

A 2.4GHz TX in 65nm CMOS defines three channels using three high-Q FBARs and supports OOK, BPSK and MSK. The oscillators have -132dBc/Hz phase noise at 1MHz offset, and are multiplexed to an efficient resonant buffer. Optimized for low output power ≈-10dBm, a fully-integrated PA implements 7.5dB dynamic output power range using a dynamic impedance transformation network, and is used for amplitude pulse-shaping. Peak PA efficiency is 44.4% and peak TX efficiency is 33%. The entire TX consumes 440pJ/bit at 1Mb/s.

4.2 pW timer for heavily duty-cycled systems

An ultra-low energy wake-up timer suitable for heavily duty-cycled systems is presented. A prototype implemented in 0.18μm CMOS consumes 4.2pW of power for 18Hz of oscillation (0.23pJ/cycle). A dynamic 3-stage architecture, duty-cycled current-source, and low operating voltage (0.6V) enabled by a voltage boost circuit all contribute to the improved efficiency.