Nathan Ickes

Physical layer driven protocol and algorithm design for energy-efficient wireless sensor networks

The potential for collaborative, robust networks of microsensors has attracted a great deal of research attention. For the most part, this is due to the compelling applications that will be enabled once wireless microsensor networks are in place; location-sensing, environmental sensing, medical monitoring and similar applications are all gaining interest. However, wireless microsensor networks pose numerous design challenges. For applications requiring long-term, robust sensing, such as military reconnaissance, one important challenge is to design sensor networks that have long system lifetimes. This challenge is especially difficult due to the energy-constrained nature of the devices. In order to design networks that have extremely long lifetimes, we propose a physical layer driven approach to designing protocols and algorithms. We first present a hardware model for our wireless sensor node and then introduce the design of physical layer aware protocols, algorithms, and applications that minimize energy consumption of the system. Our approach prescribes methods that can be used at all levels of the hierarchy to take advantage of the underlying hardware. We also show how to reduce energy consumption of non-ideal hardware through physical layer aware algorithms and protocols.

Energy-centric enabling tecumologies for wireless sensor networks

Distributed networks of thousands of collaborating microsensors promise a maintenance-free, fault-tolerant platform for gathering rich multidimensional observations of the environment. Because a microsensor node must operate for years on a tiny battery, researchers must apply innovative system-level techniques to eliminate energy inefficiencies that would have been overlooked in the past. In this article we advocate two particular enablers for energy conservation: the ability to trade off performance for energy savings within the node; and collaborative processing among nodes to reduce the overall energy dissipated in the network. New levels of energy efficiency - attained through global system-level perspectives on node and network energy consumption - will enable a future where networks of hundreds, thousands, and eventually many millions of collaborating nodes are as commonplace as todays cellular phone.

A 28 nm 0.6 V Low Power DSP for Mobile Applications

Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold (VT) variation, already a significant issue in todays advanced process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points. A new statistical static timing analysis (SSTA) methodology was also used on this design, in order to more accurately model the effects of local VT variation and achieve a reliable design with minimal pessimism.

Instruction level and operating system profiling for energy exposed software

Energy conscious software design can significantly improve the energy efficiency of a portable system. A software energy estimation technique using instruction class profiling is presented. The technique is shown to have an estimation error of less than 3% with trivial runtime overhead, based on a set of application programs evaluated on the StrongARM SA-1100 and Hitachi SH-4 microprocessors. A technique to isolate the switching and leakage energy components of software is outlined. The energy overhead of a real-time operating system is also profiled. The overall impact of system-level software energy management is quantified using the MIT /spl mu/AMPS system as an application example.

A 10-pJ/instruction, 4-MIPS micropower DSP for sensor applications

We describe a micropower DSP intended for medium bandwidth microsensor applications (such as acoustic sensing and tracking) which achieves 4 MIPS performance at 40 muW (10 pJ per instruction). Architectural optimizations for energy efficiency include a custom CPU instruction set, miniature instruction cache, hardware accelerator cores for FIR filter and FFT operations, and extensive power gating of both logic and memory.

A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip

We describe a voltage-scalable 32b microprocessor system-on-chip (SoC) that provides both moderate peak performance (up to 82.5 MHz at 1.2 V) and extreme energy efficiency (10.2 pJ/cycle at 0.54 V) for applications with limited energy budgets and time varying processing loads. The SoC employs low-voltage 8T SRAMs operating down to an array voltage of 0.4 V. Memory access energy is further reduced by miniature (128 B) latch-based instruction and data caches. On chip clock generation and the ability to boot from a small external serial flash ROM makes for a very small overall system.

Design considerations for next generation wireless power-aware microsensor nodes

In order to break the 100 /spl mu/W average power barrier of a wireless microsensor node, aggressive design methodologies need to be developed. Dynamic voltage scaling should be more aggressive, reaching subthreshold operation, and knobs should be available for adapting hardware bit-precision and latency. Since the nodes operate in a sleep state most of the time, standby leakage currents must be reduced and the power supply voltage regulated to a near-optimum value. This paper presents insight and simulation/experimental results addressing some of the challenges of designing next generation wireless microsensor nodes.

A Self-Aware Processor SoC using Energy Monitors Integrated into Power Converters for Self-Adaptation

This paper presents a self-aware processor with energy monitoring circuits that can measure actual energy consumption of the key blocks. The monitors are embedded into on-chip DC/DC converters and generate results within 10% of accuracy with minimal power (<;0.1%) and area (<;1%) overhead. Our system, which is implemented in 0.18μm technology, is designed to be voltage scalable from 1.8V down to 0.6V. Low-voltage SRAM operation is made possible through the use of 8T bit-cells and write-assists. The d-caches are designed to be re-configurable in associativity and size to adapt to compute- versus cache-bound phases of applications. Cache configuration is performed in <; 3 clock cycles including tag invalidation. These hardware features enable a software self-aware computation engine (SEEC) to dynamically adapt the processor to meet performance and energy goals. Measurement results show that up to 8.4× energy savings can be achieved with DVFS and self-adaptation.

Small-Area, Resistive Volatile Organic Compound (VOC) Sensors Using Metal–Polymer Hybrid Film Based on Oxidative Chemical Vapor Deposition (oCVD)

We report a novel room temperature methanol sensor comprised of gold nanoparticles covalently attached to the surface of conducting copolymer films. The copolymer films are synthesized by oxidative chemical vapor deposition (oCVD), allowing substrate-independent deposition, good polymer conductivity and stability. Two different oCVD copolymers are examined: poly(3,4-ethylenedioxythiophene-co-thiophene-3-aceticacid)[poly(EDOT-co-TAA)] and poly(3,4-ehylenedioxythiophene-co-thiophene-3-ethanol)[poly(EDOT-co-3-TE)]. Covalent attachment of gold nanoparticles to the functional groups of the oCVD films results in a hybrid system with efficient sensing response to methanol. The response of the poly(EDOT-co-TAA)/Au devices is found to be superior to that of the other copolymer, confirming the importance of the linker molecules (4-aminothiophenol) in the sensing behavior. Selectivity of the sensor to methanol over n-pentane, acetone, and toluene is demonstrated. Direct fabrication on a printed circuit board (PCB) is achieved, resulting in an improved electrical contact of the organic resistor to the metal circuitry and thus enhanced sensing properties. The simplicity and low fabrication cost of the resistive element, mild working temperature, together with its compatibility with PCB substrates pave the way for its straightforward integration into electronic devices, such as wireless sensor networks.

Reconfigurable processor for energy-scalable computational photography

Computational photography applications, such as lightfield photography [1], enable capture and synthesis of images that could not be captured with a traditional camera. Non-linear filtering techniques like bilateral filtering [2] form a significant part of computational photography. These techniques have a wide range of applications, including High-Dynamic Range (HDR) imaging [3], Low-Light Enhanced (LLE) imaging [4], tone management and video enhancement. The high computational complexity of such multimedia processing applications necessitates fast hardware implementations [5] to enable real-time processing. This paper describes a hardware implementation of a reconfigurable multi-application processor for computational photography.