Arun Raghunath

Framework for supporting multi-service edge packet processing on network processors

Network edge packet-processing systems, as are commonly implemented on network processor platforms, are increasingly required to support a rich set of services. These multi-service systems are also subjected to widely varying and unpredictable traffic. Current network processor systems do not simultaneously deal well with a variety of services and fluctuating workloads. For example, current methods of worst-case, static provisioning can meet performance requirements for any workload, but provisioning each service for its worst case reduces the total number of services that can be supported. Alternately, profile-driven automatic-partitioning compilers create efficient binaries for multi-service applications for specific workloads but they are sensitive to workload fluctuations. Run-time adaptation is a potential solution to this problem. With run-time adaptation, the mapping of services to system resources can be dynamically adjusted based on the workload. We have implemented an adaptive system that automatically changes the mapping of services to processors, and handles migration of services between different processor core types to match the current workload. In this paper we explain our adaptive system built on the Intelreg IXP2400 network processor. We demonstrate that it outperforms multiple different profile-driven compiled solutions for most workloads and performs within 20% of the optimal compiled solution for the remaining workloads.

Improved device driver reliability through hardware verification reuse

Faulty device drivers are a major source of operating system failures. We argue that the underlying cause of many driver faults is the separation of two highly-related tasks: device verification and driver development. These two tasks have a lot in common, and result in software that is conceptually and functionally similar, yet kept totally separate. The result is a particularly bad case of duplication of effort: the verification code is correct, but is discarded after the device has been manufactured; the driver code is inferior, but used in actual device operation. We claim that the two tasks, and the software they produce, can and should be unified, and this will result in drastic improvement of device-driver quality and reduction in the development cost and time to market. In this paper we propose a device driver design and verification workflow that achieves such unification. We apply this workflow to develop and test drivers for four different I/O devices and demonstrate that it improves the driver test coverage and allows detecting driver defects that are extremely hard to find using conventional testing techniques.

Design of a scalable network programming framework

Nearly all programmable commercial hardware solutions offered for high-speed networking systems are capable of meeting the performance and flexibility requirements of equipment vendors. However, the primary obstacle to adoption lies with the software architectures and programming environments supported by these systems. Shortcomings include use of unfamiliar languages and libraries, portability and backwards compatibility, vendor lock-in, design and development learning curve, availability of competent developers, and a small existing base of software. Another key shortcoming of previous architectures is that either they are not multi-core oriented or they expose all the hardware details, making it very hard for programmers to deal with. In this paper, we present a practical software architecture for high-speed embedded systems that is portable, easy to learn and use, multicore oriented, and efficient.

Direct data flows

Reducing power consumption of Mobile Internet Devices (MID) and smartphones is critical as battery life is a key feature for mobility. Most vendors use System-On-Chip designs integrating more and more fixed-function hardware modules in a bid to reduce power consumption. On the other hand the explosion of new applications has increased the demand for PC-like processing capabilities on these devices. They are best supported by general purpose CPUs and Operating Systems which consume more power. Traditional system architectures focus on a data transfer model with the CPU as one of the endpoints. Consequently there are numerous usage scenarios where the general purpose CPU just acts as an intermediary between hardware modules, transferring data from a hardware module to memory and vice-versa. We propose Direct Data Flows, an SoC focused system architecture where the OS can configure fixed-function hardware modules to communicate data directly with each other. This eliminates unnecessary data hops and reduces CPU interrupts allowing the general purpose CPU to be opportunistically brought into lower power states, reducing overall power consumption. We have created a prototype Direct Data Flow setup for network file downloads which demonstrates up to 65% energy savings for typical file sizes.